公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10234930B2

公开(公告)日：2019-03-19

申请号：US14621709

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US20180293493A1

公开(公告)日：2018-10-11

申请号：US15482953

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Dhiraj D. Kalamkar ,  KARTHIKEYAN VAIDYANATHAN ,  SRINIVAS SRIDHARAN ,  DIPANKAR DAS

IPC: G06N3/08 ,  G06T1/60 ,  G06T1/20

Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.

公开(公告)号：US20180293492A1

公开(公告)日：2018-10-11

申请号：US15482925

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Dhiraj D. Kalamkar ,  KARTHIKEYAN VAIDYANATHAN ,  SRINIVAS SRIDHARAN ,  DIPANKAR DAS

IPC: G06N3/08

Abstract: One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.

公开(公告)号：US09910481B2

公开(公告)日：2018-03-06

申请号：US14621731

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Daehyun Kim ,  Yuxin Bai ,  Shihao Ji ,  Sheng Li ,  Dhiraj D. Kalamkar ,  Naveen K. Mellempudi

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/32

Abstract: In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.