公开(公告)号：US10768989B2

公开(公告)日：2020-09-08

申请号：US15872762

申请日：2018-01-16

Applicant: Intel Corporation

Inventor： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC: G06F9/50 ,  G06F15/80

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10234930B2

公开(公告)日：2019-03-19

申请号：US14621709

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US09910481B2

公开(公告)日：2018-03-06

申请号：US14621731

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Daehyun Kim ,  Yuxin Bai ,  Shihao Ji ,  Sheng Li ,  Dhiraj D. Kalamkar ,  Naveen K. Mellempudi

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/32

Abstract: In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.

公开(公告)号：US09250914B2

公开(公告)日：2016-02-02

申请号：US14137218

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Camilo A. Moreno ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/00 ,  G06F9/38 ,  G06F15/80 ,  G06F12/08 ,  G06F11/07

CPC classification number: G06F9/3806 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3836 ,  G06F11/0724 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0897 ,  G06F15/80

Abstract: An apparatus and method for determining whether to execute an atomic operation locally or remotely. For example, one embodiment of a processor comprises: a decoder to decode an atomic operation on a local core; prediction logic on the local core to estimate a cost associated with execution of the atomic operation on the local core and a cost associated with execution of the atomic operation on a remote core; and the remote core to execute the atomic operation remotely if the prediction logic determines that the cost for execution on the local core is relatively greater than the cost for execution on the remote core; and the local core to execute the atomic operation locally if the prediction logic determines that the cost for local execution on the local core is relatively less than the cost for execution on the remote core.

Abstract translation: 一种用于确定是在本地还是远程执行原子操作的装置和方法。 例如，处理器的一个实施例包括：解码器，用于解码局部核心上的原子操作; 本地核心上的预测逻辑来估计与本地核心上的原子操作的执行相关的成本以及与在远程核心上执行原子操作相关联的成本; 以及所述远程核心，如果所述预测逻辑确定所述本地核上的执行成本相对大于所述远程核上的执行成本，则远程执行所述原子操作; 如果预测逻辑确定本地核心上的本地执行成本相对低于在远程核心上执行的成本，本地核心将在本地执行原子操作。

公开(公告)号：US20150178200A1

公开(公告)日：2015-06-25

申请号：US14585573

申请日：2014-12-30

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/08

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract translation: 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。

公开(公告)号：US10303606B2

公开(公告)日：2019-05-28

申请号：US15465097

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M. Yoo

IPC: G06F12/0813 ,  G06F12/0817 ,  G06F12/0831

Abstract: Technologies for migration of dynamic home tile mapping are described. A cache controller can receive coherence messages from other processor cores on the die. The cache controller records locations from which the coherence messages originate and determine distances between the requested home tiles and the locations from which the coherence messages originate. The cache controller determines whether an average distance between a particular home tile, whose identifier is stored in the home tile table, exceeds a threshold. When the average distance exceeds the defined threshold, the cache controller migrates the particular home tile to another location.

公开(公告)号：US20190026158A1

公开(公告)日：2019-01-24

申请号：US15872762

申请日：2018-01-16

Applicant: Intel Corporation

Inventor： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC: G06F9/50 ,  G06F15/80

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

公开(公告)号：US20170242700A1

公开(公告)日：2017-08-24

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621 ,  Y02D10/13

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US09740623B2

公开(公告)日：2017-08-22

申请号：US13993034

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Daehyun Kim ,  Jong Soo Park ,  Richard M Yoo ,  Ganesh Bikshandi

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/127

CPC classification number: G06F12/0891 ,  G06F12/023 ,  G06F12/127 ,  Y02D10/13

Abstract: A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.