公开(公告)号：US20190318225A1

公开(公告)日：2019-10-17

申请号：US16454318

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Alexander Heinecke ,  Evangelos Georganas ,  Justin Gottschlich

IPC: G06N3/04 ,  G06N3/08 ,  G06F9/30

Abstract: An example includes a sequence generator to generate a plurality of sequence pairs, a first one of the sequence pairs including: (i) a first input sequence representing first accesses to first tensors in a first loop nest of a first computer program, and (ii) a first output sequence representing a first tuned loop nest corresponding to the first accesses to the first tensors in the first loop nest; a model trainer to train a recurrent neural network based on the sequence pairs as training data, the recurrent neural network to be trained to tune loop ordering of a second computer program based on a second input sequence representing second accesses to a second tensor in a second loop nest of the second computer program; and a memory interface to store, in memory, a trained model corresponding to the recurrent neural network.

公开(公告)号：US20190317805A1

公开(公告)日：2019-10-17

申请号：US16451974

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Thijs Metsch ,  Joseph Butler ,  Mohammad Mejbah Ul Alam ,  Justin Gottschlich

IPC: G06F9/48 ,  G06N20/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that optimize workflows. An example apparatus includes an intent determiner to determine an objective of a user input, the objective indicating a task to be executed in an infrastructure, a configuration composer to compose a plurality of workflows based on the determined objective, a model executor to execute a machine learning model to create a confidence score relating to the plurality of workflows, and a workflow selector to select at least one of the plurality of workflows for execution in the infrastructure, the selection of the at least one of the plurality of workflows based on the confidence score.

公开(公告)号：US20190256088A1

公开(公告)日：2019-08-22

申请号：US16399967

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Sridhar Sharma ,  Patrick Mead ,  Ignacio Alvarez ,  Kathiravetpillai Sivanesan ,  Justin Gottschlich ,  Shahab Layeghi ,  Liuyang Lily Yang

IPC: B60W30/09 ,  B60W30/095 ,  B60W50/14 ,  G06K9/00

Abstract: Methods and apparatus to generate vehicle warnings are disclosed. An example apparatus includes a sensor to detect a vehicle, where the sensor is associated with an observer of the vehicle, an object tracker to determine a motion of the vehicle, an accident estimator to calculate a likelihood of a collision of the vehicle based on the determined motion, and a transceiver to transmit a message to the vehicle upon the likelihood of the collision exceeding a threshold, where the message includes information pertaining to the collision.

公开(公告)号：US10387296B2

公开(公告)日：2019-08-20

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano Pereira

IPC: G06F9/44 ,  G06F11/00 ,  G06F9/46 ,  G06F11/36 ,  G06F8/70 ,  G06F8/41 ,  G06F9/448

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

公开(公告)号：US20150363306A1

公开(公告)日：2015-12-17

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai

IPC: G06F11/36 ,  G06F9/44

CPC classification number: G06F11/3688 ,  G06F8/434 ,  G06F8/70 ,  G06F9/448 ,  G06F11/36 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/3672

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Abstract translation: 公开了用于识别负责在具有多个同时执行的线程的计算机程序中引起并发错误的线程的方法和系统。 本文公开的示例性方法包括使用处理器来定义数据类型。 所述数据类型包括第一谓词，使用插入在所述多个线程的第一线程中的第一程序指令来调用所述第一谓词，第二谓词，所述第二谓词使用插入到所述第一线索的第二线程中的第二程序指令来调用 多个线程，以及定义第一谓词和第二谓词之间的关系的表达式。 该方法还包括响应于确定在执行计算机程序期间的关系得到满足，识别第一线程和第二线程，以负责并发错误。

公开(公告)号：US11727265B2

公开(公告)日：2023-08-15

申请号：US16455346

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Ignacio Javier Alvarez ,  Javier Felip Leon ,  David Israel Gonzalez Aguirre ,  Javier Sebastian Turek ,  Luis Carlos Maria Remis ,  Justin Gottschlich

IPC: G06N3/08 ,  G06N3/045

CPC classification number: G06N3/08 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture to provide machine programmed creative support to a user are disclosed. An example apparatus include an artificial intelligence architecture to be trained based on previous inputs of the user; a processor to: implement a first machine learning model based on the trained artificial intelligence architecture; and predict a first action based on a current state of a computer program using the first machine learning model; implement a second machine learning model based on the trained artificial intelligence architecture; and predict a second action based on the current state of the computer program using the second machine learning model; and a controller to select a state based on the action that results in a state that is more divergent from the current state of the computer program.

公开(公告)号：US11704226B2

公开(公告)日：2023-07-18

申请号：US17483431

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Niranjan Hasabnis ,  Justin Gottschlich ,  Jeremie Dreyfuss ,  Amitai Armon ,  Itamar Ben-Ari ,  Oren David Kimhi

IPC: G06F9/44 ,  G06F11/36 ,  G06F8/40 ,  G06F8/73

CPC classification number: G06F11/3648 ,  G06F8/40 ,  G06F8/73

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to detect code defects. An example apparatus includes repository interface circuitry to retrieve code repositories corresponding to a programming language of interest, tree generating circuitry to generate parse trees corresponding to code blocks contained in the code repositories, directed acyclic graph (DAG) circuitry to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information, abstraction generating circuitry to abstract the DAGs, invariant identification circuitry to extract invariants from the abstracted DAGs, and DAG comparison circuitry to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

公开(公告)号：US11656903B2

公开(公告)日：2023-05-23

申请号：US16451974

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Thijs Metsch ,  Joseph Butler ,  Mohammad Mejbah Ul Alam ,  Justin Gottschlich

IPC: G06F9/46 ,  G06F9/48 ,  G06N20/00

CPC classification number: G06F9/4881 ,  G06N20/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that optimize workflows. An example apparatus includes an intent determiner to determine an objective of a user input, the objective indicating a task to be executed in an infrastructure, a configuration composer to compose a plurality of workflows based on the determined objective, a model executor to execute a machine learning model to create a confidence score relating to the plurality of workflows, and a workflow selector to select at least one of the plurality of workflows for execution in the infrastructure, the selection of the at least one of the plurality of workflows based on the confidence score.

公开(公告)号：US20230031591A1

公开(公告)日：2023-02-02

申请号：US17853176

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Luis Carlos Maria Remis ,  Ignacio Javier Alvarez ,  Li Chen ,  Javier Felip Leon ,  David Israel Gonzalez Aguirre ,  Justin Gottschlich ,  Javier Sebastian Turek

IPC: G06F16/9032 ,  G06F16/2457 ,  G06F16/9038

Abstract: Methods and apparatus to facilitate generation of database queries are disclosed. An example apparatus includes a generator to generate a global importance tensor. The global importance tensor based on a knowledge graph representative of information stored in a database. The knowledge graph includes objects and connections between the objects. The global importance tensor includes importance values for different types of the connections between the objects. The example apparatus further includes an importance adaptation analyzer to generate a session importance tensor based on the global importance tensor and a user query, and a user interface to provide a suggested query to a user based on the session importance tensor.

公开(公告)号：US11507838B2

公开(公告)日：2022-11-22

申请号：US16456863

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Mikael Bourges-Sevenier ,  Adam Herr ,  Sridhar Sharma ,  Derek Gerstmann ,  Todd Anderson ,  Justin Gottschlich

IPC: G06N3/08 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.