公开(公告)号：US20200066622A1

公开(公告)日：2020-02-27

申请号：US16107920

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01G4/33 ,  H01G4/228

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.

公开(公告)号：US20200027856A1

公开(公告)日：2020-01-23

申请号：US16586820

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20190244922A1

公开(公告)日：2019-08-08

申请号：US16386195

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Amanda E. SCHUCKMAN ,  Steve S. CHO

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/498 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H05K1/00 ,  H01L2924/00

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.