公开(公告)号：US20240258183A1

公开(公告)日：2024-08-01

申请号：US18632047

申请日：2024-04-10

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20200168569A1

公开(公告)日：2020-05-28

申请号：US16481385

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Sai VADLAMANI ,  Aleksandar ALEKSOV ,  Rahul JAIN ,  Kyu Oh LEE ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Telesphor KAMGAING

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：US20200006005A1

公开(公告)日：2020-01-02

申请号：US16024715

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Andrew J. BROWN ,  Prithwish CHATTERJEE ,  Sai VADLAMANI ,  Lauren LINK

IPC: H01G4/33 ,  H01L49/02 ,  H01L23/522

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

公开(公告)号：US20220328431A1

公开(公告)日：2022-10-13

申请号：US17852003

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20210066162A1

公开(公告)日：2021-03-04

申请号：US16557896

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Sergio A. CHAN ARGUEDAS ,  Nicholas S. HAEHN ,  Edvin CETEGEN ,  Nicholas NEAL ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON ,  Vipul MEHTA

IPC: H01L23/42 ,  H01L23/00

Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

公开(公告)号：US20210020532A1

公开(公告)日：2021-01-21

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Edvin CETEGEN ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US20210020531A1

公开(公告)日：2021-01-21

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240063173A1

公开(公告)日：2024-02-22

申请号：US18385167

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16235 ,  H01L2224/16113

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20230245940A1

公开(公告)日：2023-08-03

申请号：US18133868

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/53295 ,  H01L23/3128 ,  H01L24/06 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2224/83051 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220359115A1

公开(公告)日：2022-11-10

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.