公开(公告)号：US20190206822A1

公开(公告)日：2019-07-04

申请号：US15859481

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ji Yong PARK ,  Kyu Oh LEE ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11019 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11831 ,  H01L2224/13008 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81138 ,  H05K3/4007 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/013

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.

公开(公告)号：US20240063173A1

公开(公告)日：2024-02-22

申请号：US18385167

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16235 ,  H01L2224/16113

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20230245940A1

公开(公告)日：2023-08-03

申请号：US18133868

申请日：2023-04-12

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/53295 ,  H01L23/3128 ,  H01L24/06 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2224/83051 ,  H01L2224/81

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200168569A1

公开(公告)日：2020-05-28

申请号：US16481385

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Sai VADLAMANI ,  Aleksandar ALEKSOV ,  Rahul JAIN ,  Kyu Oh LEE ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Telesphor KAMGAING

IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：US20190189582A1

公开(公告)日：2019-06-20

申请号：US16328135

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Kyu Oh LEE ,  Yi LI ,  Yueli LIU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  B23K35/0238 ,  B23K35/0244 ,  B23K35/24 ,  B23K35/262 ,  C22C13/00 ,  H01L23/00 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13247 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

公开(公告)号：US20150318238A1

公开(公告)日：2015-11-05

申请号：US14798395

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Mark S. HLAD ,  Islam A. SALAMA ,  Mihir K. ROY ,  Tao WU ,  Yueli LIU ,  Kyu Oh LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20250149501A1

公开(公告)日：2025-05-08

申请号：US19013849

申请日：2025-01-08

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20240186202A1

公开(公告)日：2024-06-06

申请号：US18415268

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/53295 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210398941A1

公开(公告)日：2021-12-23

申请号：US17466842

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20200266149A1

公开(公告)日：2020-08-20

申请号：US16646932

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng XU ,  Junnan ZHAO ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.