公开(公告)号：US12141578B2

公开(公告)日：2024-11-12

申请号：US17115989

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/544 ,  G06F9/38 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G09G5/393 ,  G06F17/16 ,  G06N20/00 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US11080046B2

公开(公告)日：2021-08-03

申请号：US17169232

申请日：2021-02-05

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/302 ,  G06F7/483 ,  G06N3/04 ,  G06F17/16 ,  G06F9/30 ,  G09G5/393 ,  G06F7/544 ,  G06F9/38 ,  G06N3/08 ,  G06N3/063 ,  G06N20/00 ,  G06T15/00

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

公开(公告)号：US10599429B2

公开(公告)日：2020-03-24

申请号：US16003545

申请日：2018-06-08

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Sanu Mathew

IPC: G06F9/30 ,  G06F17/16 ,  G06N20/00 ,  G06N3/063

Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.

公开(公告)号：US10353706B2

公开(公告)日：2019-07-16

申请号：US15819152

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G09G5/393 ,  G06N3/08 ,  G06N3/063 ,  G06T15/00 ,  G06N20/00

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US20180167199A1

公开(公告)日：2018-06-14

申请号：US15374700

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Sanu K. Mathew ,  Mark A. Anders ,  Jesse Walker ,  Jason G. Sandri

IPC: H04L9/06 ,  G06F12/14

CPC classification number: H04L9/0643 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1408 ,  G06F17/50 ,  G06F2212/1052 ,  G06F2212/6026 ,  G09C1/00 ,  H04L9/0618 ,  H04L9/0625

Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.

公开(公告)号：US09992042B2

公开(公告)日：2018-06-05

申请号：US14574189

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Gregory K. Chen

IPC: H04L12/66 ,  H04L12/64 ,  H04L12/933 ,  H04L12/50 ,  H04L12/24 ,  G06F15/78

CPC classification number: H04L12/64 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6418 ,  H04L12/66 ,  H04L41/02 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request.

公开(公告)号：US09979668B2

公开(公告)日：2018-05-22

申请号：US14579303

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Aaron T. Stillmaker

IPC: H04L12/863 ,  H04L12/911 ,  H04L12/935 ,  G06F15/78

CPC classification number: H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

公开(公告)号：US09923730B2

公开(公告)日：2018-03-20

申请号：US14574294

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/28 ,  H04L12/18 ,  H04L12/761 ,  H04L12/933 ,  H04L12/935

CPC classification number: H04L12/1886 ,  H04L45/16 ,  H04L49/109 ,  H04L49/3009

Abstract: A multicast message that is to originate from a source is received. The multicast message comprises an identifier. A plurality of directions in which the multicast message is to fork at the router are stored. A plurality of messages from the directions in which the multicast message is to fork are received. The received messages are to comprise the identifier. The plurality of messages are aggregated into an aggregate message and sent towards the source.

公开(公告)号：US09652425B2

公开(公告)日：2017-05-16

申请号：US14126910

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Sudhir K. Satpathy ,  Ram K. Krishnamurthy

IPC: G06F13/42 ,  G06F13/40 ,  H04L12/933

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F15/7825 ,  H04L12/46 ,  H04L49/109 ,  H04L67/10 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.

公开(公告)号：US20160182396A1

公开(公告)日：2016-06-23

申请号：US14574258

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Gregory K. Chen ,  Mark A. Anders

IPC: H04L12/913 ,  H04L12/935 ,  H04L12/933

CPC classification number: H04L47/724 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6402 ,  H04L12/66 ,  H04L49/109 ,  H04L49/3018 ,  H04L49/3027

Abstract: An apparatus may comprise a plurality of ports and a plurality of channel reservation banks A channel reservation bank is to be associated with a port of the plurality of ports. The channel reservation bank is to comprise a plurality of channel reservation slots. The port of the plurality of ports is to comprise a plurality of circuit-switched channels through the port. The configuration of each of the plurality of circuit-switched channels to be based on information stored in a channel reservation slot of the channel reservation bank to be associated with the port.

Abstract translation: 装置可以包括多个端口和多个信道预留库。信道预留库将与多个端口的端口相关联。 信道预约库包括多个信道预留时隙。 多个端口的端口包括通过端口的多个电路交换信道。 多个电路交换信道中的每一个的配置将基于存储在与端口相关联的信道预留库的信道预留时隙中的信息。