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    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH
    1.
    发明公开
    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH 审中-公开

    公开(公告)号：US20240223167A1

    公开(公告)日：2024-07-04

    申请号：US18091970

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram K. Krishnamurthy

    IPC: H03K4/94 ,  H03K3/037

    CPC classification number: H03K4/94 ,  H03K3/037 ,  H03K19/20

    Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

    PATTERN MATCHING CIRCUIT
    3.
    发明申请
    PATTERN MATCHING CIRCUIT 审中-公开

    公开(公告)号：US20170286420A1

    公开(公告)日：2017-10-05

    申请号：US15085816

    申请日：2016-03-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Kaushik Vaidyanathan ,  Ram K. Krishnamurthy

    IPC: G06F17/30 ,  G06F21/56

    CPC classification number: G06F16/9014 ,  Y02D10/45

    Abstract: Embodiments include a pattern matching circuit that implements a Bloom filter including one or more hash functions. The hash functions may generate respective addresses corresponding to bits of a memory array. Various techniques for improving the area and/or power efficiency of the pattern matching circuit are disclosed. For example, a number of logic 1 bits per column of hash matrixes associated with the one or more hash functions may be restricted to a pre-defined number. A plurality of addresses generated by the hash functions may use the same column address to correspond to bits of a same column. A single read port memory may be used to simultaneously read two bits and generate an output signal that indicates whether the two bits are both a first logic value. Other embodiments may be described and claimed.

    ADAPTIVELY SWITCHED NETWORK-ON-CHIP
    4.
    发明申请
    ADAPTIVELY SWITCHED NETWORK-ON-CHIP 有权
    适应性切换的网络芯片

    公开(公告)号：US20160182405A1

    公开(公告)日：2016-06-23

    申请号：US14579729

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul ,  Ram K. Krishnamurthy ,  Yejoong Kim

    IPC: H04L12/933 ,  H04L12/911

    CPC classification number: H04L49/109 ,  H04L45/60 ,  H04L49/60

    Abstract: A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.

    Abstract translation: 接收与第一数据流相关联的分组交换预约请求。 选择通信模式。 通信模式是电路交换模式或分组交换模式。 根据通信模式来传送第一数据流的至少一部分。

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