公开(公告)号：US12014959B2

公开(公告)日：2024-06-18

申请号：US17516560

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823456 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66484 ,  H01L29/7831

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US11961836B2

公开(公告)日：2024-04-16

申请号：US16147205

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hyung-Jin Lee ,  Mark Armstrong ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Ayan Kar

IPC: H01L27/08 ,  H01L29/66 ,  H01L29/93 ,  H10B99/00

CPC classification number: H01L27/0808 ,  H01L29/66174 ,  H01L29/93 ,  H10B99/00

Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

公开(公告)号：US20230369426A1

公开(公告)日：2023-11-16

申请号：US17742636

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Van H. Le ,  Timothy Jen ,  Kamal H. Baloch ,  Mark Armstrong ,  Albert B. Chen ,  Moshe Dolejsi ,  Shailesh Kumar Madisetti ,  Afrin Sultana ,  Deepyanti Taneja ,  Vishak Venkatraman

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10805

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

公开(公告)号：US20200312838A1

公开(公告)日：2020-10-01

申请号：US16368671

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Akm Ahsan ,  Mark Armstrong ,  Guannan Liu

IPC: H01L27/02 ,  H01L27/06 ,  H01L21/8249

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

公开(公告)号：US09859368B2

公开(公告)日：2018-01-02

申请号：US15333123

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US12205947B2

公开(公告)日：2025-01-21

申请号：US18207065

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Guannan Liu ,  Akm A. Ahsan ,  Mark Armstrong ,  Bernhard Sell

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US11715787B2

公开(公告)日：2023-08-01

申请号：US17514058

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/266 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US11515424B2

公开(公告)日：2022-11-29

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US11205715B2

公开(公告)日：2021-12-21

申请号：US16632856

申请日：2017-08-21

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US10580860B2

公开(公告)日：2020-03-03

申请号：US16358613

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3115 ,  B82Y40/00

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.