公开(公告)号：US20250112216A1

公开(公告)日：2025-04-03

申请号：US18478937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Georgios C. Dogiamis ,  Said Rami ,  Adel Elsherbini

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more thick gate oxide transistors, group III-V transistors, varactors, or electrostatic discharge protection devices. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US11108433B2

公开(公告)日：2021-08-31

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420578A1

公开(公告)日：2023-12-28

申请号：US17848660

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

Abstract: A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

公开(公告)号：US11621334B2

公开(公告)日：2023-04-04

申请号：US16260600

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Surej Ravikumar ,  Kinyip Phoa

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L27/12 ,  G06F13/10

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

公开(公告)号：US20200259018A1

公开(公告)日：2020-08-13

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US20230299123A1

公开(公告)日：2023-09-21

申请号：US17698939

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Qiang Yu ,  Gwang-Soo Kim ,  Said Rami

IPC: H01L49/02 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L28/10 ,  H01L24/08 ,  H01L23/5227 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/06051 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0613 ,  H01L25/0652

Abstract: In one embodiment, an apparatus includes a first integrated circuit die with metal bonding pads that are co-planar with an external surface of the die and a second integrated circuit die with metal bonding pads that are co-planar with an external surface of the die. The first and second integrated circuit dies are coupled together such that their external surfaces are in contact and the metal pads of the first integrated circuit die are in direct contact with respective metal pads of the second integrated circuit die. The apparatus also includes an inductor formed at least partially by the metal pads of the first integrated circuit die and the metal pads of the second integrated circuit die.

公开(公告)号：US11515424B2

公开(公告)日：2022-11-29

申请号：US16270826

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

公开(公告)号：US20190115951A1

公开(公告)日：2019-04-18

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.