公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20230207560A1

公开(公告)日：2023-06-29

申请号：US17561244

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Nicholas Minutillo ,  Ryan Cory Haislmaier ,  Yulia Tolstova ,  Yoon Jung Chang ,  Tahir Ghani ,  Szuya S. Liao ,  Anand Murthy ,  Pratik Patel

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823412

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.

公开(公告)号：US20230197840A1

公开(公告)日：2023-06-22

申请号：US17557827

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Xiaoye Qin ,  Johann C. Rode ,  Atsunori Tanaka ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

公开(公告)号：US20200098757A1

公开(公告)日：2020-03-26

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.