公开(公告)号：US20230197840A1

公开(公告)日：2023-06-22

申请号：US17557827

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Xiaoye Qin ,  Johann C. Rode ,  Atsunori Tanaka ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

公开(公告)号：US11552169B2

公开(公告)日：2023-01-10

申请号：US16367134

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Ryan Keech ,  Nicholas G. Minutillo ,  Suresh Vishwanath

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/66 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08

Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US12154898B2

公开(公告)日：2024-11-26

申请号：US17133024

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Avyaya Jayanthinarasimham ,  Brian Greene ,  Suresh Vishwanath

IPC: H01L27/07 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

公开(公告)号：US11621325B2

公开(公告)日：2023-04-04

申请号：US16368097

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Suresh Vishwanath

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L21/40 ,  H01L29/417 ,  H01L27/092 ,  H01L29/36

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US12046654B2

公开(公告)日：2024-07-23

申请号：US16912118

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Dan S. Lavric ,  Glenn A. Glass ,  Thomas T. Troeger ,  Suresh Vishwanath ,  Jitendra Kumar Jha ,  John F. Richards ,  Anand S. Murthy ,  Srijit Mukherjee

IPC: H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US12027417B2

公开(公告)日：2024-07-02

申请号：US16913320

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Suresh Vishwanath ,  Yulia Tolstova ,  Pratik Patel ,  Szuya S. Liao ,  Anand S. Murthy

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/76834 ,  H01L21/02532 ,  H01L21/28255 ,  H01L21/3215 ,  H01L21/76831 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66628

Abstract: Integrated circuit structures having source or drain structures with a high germanium concentration capping layer are described. In an example, an integrated circuit structure includes source or drain structures including an epitaxial structure embedded in a fin at a side of a gate stack. The epitaxial structure has a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer with an abrupt interface between the capping semiconductor layer and the lower semiconductor layer. The lower semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of less than 40% at the abrupt interface. The capping semiconductor layer includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 50% at the abrupt interface and throughout the capping semiconductor layer.

公开(公告)号：US20220199615A1

公开(公告)日：2022-06-23

申请号：US17133024

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Avyaya JAYANTHINARASIMHAM ,  Brian GREENE ,  Suresh Vishwanath

IPC: H01L27/07 ,  H01L27/088 ,  H01L29/861 ,  H01L29/78 ,  H01L29/06

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

公开(公告)号：US12288808B2

公开(公告)日：2025-04-29

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US12027585B2

公开(公告)日：2024-07-02

申请号：US18110315

申请日：2023-02-15

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Suresh Vishwanath

IPC: H01L29/08 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

公开(公告)号：US11804523B2

公开(公告)日：2023-10-31

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/785

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.