公开(公告)号：US20190196988A1

公开(公告)日：2019-06-27

申请号：US15855798

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Omid Azizi ,  Chandan Egbert ,  Amin Firoozshahian ,  David Christopher Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Ashok Raj ,  Alexandre Solomatnikov ,  Stephen Van Doren

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F2213/24

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

公开(公告)号：US20220004597A1

公开(公告)日：2022-01-06

申请号：US17481064

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Omid Azizi

IPC: G06F17/16 ,  G06N20/00 ,  G06F9/30 ,  G06F9/38

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：US11126690B2

公开(公告)日：2021-09-21

申请号：US16370094

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Omid Azizi

IPC: G06F17/16 ,  G06N20/00 ,  G06F9/30 ,  G06F9/38

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：US10733108B2

公开(公告)日：2020-08-04

申请号：US15980523

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Vijay Bahirji ,  Amin Firoozshahian ,  Mahesh Madhav ,  Toby Opferman ,  Omid Azizi

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/02

Abstract: A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.