公开(公告)号：US10354033B2

公开(公告)日：2019-07-16

申请号：US15711740

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： Cristian Florin Dumitrescu ,  Jasvinder Singh ,  Patrick Lu

IPC: G06F17/50 ,  G06F9/54 ,  G06F9/50 ,  H04L29/06

Abstract: One embodiment provides a system to identify a “best” usage of a given set of CPU cores to maximize performance of a given application. The given application is parsed into a number of functional blocks, and the system maps the functional blocks to the given set of CPU cores to maximize the performance of the given application. The system determines and then tests various mappings to determine the performance, generally preferring mappings that maximize throughput per physical core. Before testing a mapping, the system determines whether the mapping is redundant with any previously tested mappings. In addition, given a performance target for the given application, the system determines a minimum number of CPU cores needed for the application to meet the application performance target.

公开(公告)号：US10241885B2

公开(公告)日：2019-03-26

申请号：US15460385

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/34 ,  G06F11/30 ,  H03K19/177

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

公开(公告)号：US10229060B2

公开(公告)日：2019-03-12

申请号：US15369594

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Ren Wang ,  Namakkal N. Venkatesan ,  Patrick Lu

IPC: G06F12/0862

Abstract: Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected information to the cache, and a prefetch tuning buffer including tuning state for the set of candidate prefetcher algorithms, wherein the prefetcher is to adjust operation of the prefetcher algorithm based on the tuning state.

公开(公告)号：US20190004954A1

公开(公告)日：2019-01-03

申请号：US15640283

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Thomas Willhalm ,  Patrick Lu ,  Francesc Guim Bernat ,  Shrikant M. Shah

IPC: G06F12/0862 ,  G06F12/02

Abstract: Devices and systems having memory-side adaptive prefetch decision-making, including associated methods, are disclosed and described. Adaptive information can be provided to memory-side controller and prefetch components that allow such memory-side components to prefetch data in a manner that is adaptive with respect to a particular read memory request or to a thread performing read memory requests.

公开(公告)号：US20180285260A1

公开(公告)日：2018-10-04

申请号：US15476866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm

IPC: G06F12/06 ,  G06F12/0873 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/0638 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0891 ,  G06F13/1694 ,  G06F13/4239 ,  G06F2212/7201

Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

公开(公告)号：US20180267878A1

公开(公告)日：2018-09-20

申请号：US15460385

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/34 ,  G06F11/30 ,  H03K19/177

CPC classification number: G06F11/3409 ,  G06F11/3017 ,  H03K19/1776 ,  H03K19/17764

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

公开(公告)号：US12271308B2

公开(公告)日：2025-04-08

申请号：US18399553

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Priya Autee ,  Abhishek Khade ,  Patrick Lu ,  Edwin Verplanke ,  Vivekananthan Sanjeepan

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US20200081718A1

公开(公告)日：2020-03-12

申请号：US16680907

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US10521236B2

公开(公告)日：2019-12-31

申请号：US15940408

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Christopher Wilkerson ,  Binh Pham ,  Patrick Lu ,  Jared Warner Stark, IV

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

公开(公告)号：US20190042432A1

公开(公告)日：2019-02-07

申请号：US15992557

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： Abhishek Khade ,  Patrick Lu ,  Francesc Guim Bernat

IPC: G06F12/0846

Abstract: There is disclosed in one example a computing apparatus, including: a cache; a caching agent (CA); an integrated input/output (IIO) block to provide a cache coherent interface to a peripheral device at a first speed; a core configured to poll an address within the cache via the CA, wherein the address is to receive incoming data from the peripheral device via the IIO, and wherein the core is capable of polling the address at a second speed substantially greater than the first speed; and a hardware uncore agent configured to: identify a collision between the core and the IIO including determining that the core is polling the address at a rate that is determined to interfere with access to the address by the IIO; and throttle the core's access to the address.