公开(公告)号：US10579382B2

公开(公告)日：2020-03-03

申请号：US15879416

申请日：2018-01-24

Applicant: Intel Corporation

Inventor： Rajesh Sankaran ,  Ankur Shah ,  Bryan White ,  Hema Nalluri ,  David Puffer ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale ,  Balaji Vembu

IPC: G06F9/30 ,  G06F9/32 ,  G06T1/20 ,  G06F12/1009

Abstract: An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

公开(公告)号：US12248800B2

公开(公告)日：2025-03-11

申请号：US17561433

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran ,  Hisham Shafi

IPC: G06F9/455 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

公开(公告)号：US12164444B2

公开(公告)日：2024-12-10

申请号：US17357829

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/455

Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

公开(公告)号：US12099841B2

公开(公告)日：2024-09-24

申请号：US17212977

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Rajesh Sankaran ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David Koufaty

IPC: G06F9/54 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/30076 ,  G06F9/30101 ,  G06F9/4825

Abstract: An embodiment of an apparatus comprises decode circuitry to decode a single instruction, the single instruction to include a field for an identifier of a first source operand, a field for an identifier of a destination operand, and a field for an opcode, the opcode to indicate execution circuitry is to program a user timer, and execution circuitry to execute the decoded instruction according to the opcode to retrieve timer program information from a location indicated by the first source operand, and program a user timer indicated by the destination operand based on the retrieved timer program information. Other embodiments are disclosed and claimed.

公开(公告)号：US11740931B2

公开(公告)日：2023-08-29

申请号：US17651906

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Ashok Raj ,  Rajesh Sankaran

IPC: G06F9/48 ,  G06F13/28 ,  G06F9/30

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/485 ,  G06F13/28

Abstract: A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to control the interface and to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.

公开(公告)号：US20230205563A1

公开(公告)日：2023-06-29

申请号：US17560826

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Anjali Singhai Jain ,  Patrick Maloney

IPC: G06F9/455 ,  G06F12/0831

CPC classification number: G06F9/45558 ,  G06F12/0835 ,  G06F2009/45583 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45591

Abstract: Systems, methods, and devices for efficient I/O page fault handling are provided. A system may include a peripheral device that accesses guest memory of a virtual machine using direct memory access (DMA) and a processing device that that runs the virtual machine. The processing device may include a buffer allocated to receive a payload from the peripheral device while an input/output page fault corresponding to a page of the guest memory is resolved. The processing device may also include an input/output page fault queue to store a descriptor corresponding to the input/output page fault and a fault buffer queue to store a descriptor corresponding to a location of the buffer allocated to receive the payload while the input/output page fault is resolved.

公开(公告)号：US20220414029A1

公开(公告)日：2022-12-29

申请号：US17357829

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Rajesh Sankaran ,  Rupin Vakharwala ,  Utkarsh Y. Kakaiya

IPC: G06F13/16 ,  G06F13/42

Abstract: Techniques and mechanisms for an input-output memory management module (IOMMU) to indicate to software whether a page request by an endpoint device is to be serviced. In an embodiment, the IOMMU receives from the endpoint device a response to an invalidation wait message. Based on the response, the IOMMU provides first information which indicates to software that page requests have been flushed from the endpoint device. Page request message from the endpoint device are compatible with an interface standard which also comprises a stop marker message type. The first information is provided independent of the endpoint device providing any message which is of the stop marker message type. In another embodiment, the first information includes a drain marker generated by the IOMMU, or a snapshot of an address corresponding to an end of a page request queue.

公开(公告)号：US11526290B2

公开(公告)日：2022-12-13

申请号：US16458013

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： David Koufaty ,  Rajesh Sankaran ,  Rupin Vakharwala

IPC: G06F3/06 ,  G06F12/0882 ,  G06F12/1009

Abstract: A system for tracking memory access patterns to be used in making data placement and migration policies. The system includes a processing unit and a system memory. The system memory includes a local memory and a remote memory, each of which having mapped thereon, a plurality of memory pages. Each of the plurality of memory pages corresponds to one or more physical addresses. A set of attributes for each memory page is stored in a physical attribute table (PAT). The PAT is looked up and the attributes updated when a memory access is detected. Attributes stored in the PAT are used to control the movement of memory pages between the local memory and the remote memory. When the attributes in the PAT indicate a remote memory page is being accessed frequently by the processing unit, the remote memory page is moved from the remote memory to the local memory.

公开(公告)号：US11513957B2

公开(公告)日：2022-11-29

申请号：US17027248

申请日：2020-09-21

Applicant: Intel Corporation

Inventor： Ren Wang ,  Andrew J. Herdrich ,  Yen-cheng Liu ,  Herbert H. Hum ,  Jong Soo Park ,  Christopher J. Hughes ,  Namakkal N. Venkatesan ,  Adrian C. Moga ,  Aamer Jaleel ,  Zeshan A. Chishti ,  Mesut A. Ergin ,  Jr-shian Tsai ,  Alexander W. Min ,  Tsung-yuan C. Tai ,  Christian Maciocco ,  Rajesh Sankaran

IPC: G06F12/0842 ,  G06F12/0893 ,  G06F12/109 ,  G06F12/0813 ,  G06F12/0831 ,  G06F9/455

Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

公开(公告)号：US11228539B2

公开(公告)日：2022-01-18

申请号：US16540807

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Sugesh Chandran ,  Parthasarathy Sarangam ,  Sujoy Sen ,  Susanne M. Balle ,  Rajesh Sankaran

IPC: H04L12/931 ,  H04L29/12 ,  H04L12/06 ,  G06F30/34

Abstract: Technologies for network interface controllers (NICs) include a compute sled and an accelerator sled in communication over a network. The accelerator sled configures a virtual switch endpoint associated with a remote direct memory access (RDMA) server instance that is associated with a field-programmable gate array (FPGA) of the accelerator sled. The accelerator sled updates local software defined networking (SDN) tables with a virtual tunnel associated with the virtual switch endpoint and a remote compute sled. A virtual switch of the accelerator sled switches virtual tunnel traffic from the remote compute sled to the RDMA server instance, which transfers data to or from the FPGA. The compute sled also updates a local SDN table with the virtual tunnel, and a virtual switch of the compute sled switches virtual tunnel traffic to or from the accelerator sled. Other embodiments are described and claimed.