公开(公告)号：US20220199468A1

公开(公告)日：2022-06-23

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L23/00 ,  H01L27/22 ,  H01L27/24

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US11189730B2

公开(公告)日：2021-11-30

申请号：US16649716

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US12266570B2

公开(公告)日：2025-04-01

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US12199142B2

公开(公告)日：2025-01-14

申请号：US17133092

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Jack T. Kavalieros ,  Stephen M. Cea ,  Ashish Agrawal ,  Willy Rachmady

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20240006506A1

公开(公告)日：2024-01-04

申请号：US17856979

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Jack T. Kavalieros ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/458 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Phosphide and arsenide metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting the amount of contact metal that diffuses into source/drain regions.

公开(公告)号：US11699756B2

公开(公告)日：2023-07-11

申请号：US17541199

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7846 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42364

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US11575005B2

公开(公告)日：2023-02-07

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US20190305085A1

公开(公告)日：2019-10-03

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US20190273133A1

公开(公告)日：2019-09-05

申请号：US16347110

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Glenn A. Glass ,  Van H. Le ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Willy Rachmady

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10

Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

公开(公告)号：US12255234B2

公开(公告)日：2025-03-18

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.