公开(公告)号：US11024713B2

公开(公告)日：2021-06-01

申请号：US16465758

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Glenn A. Glass ,  Harold W. Kennel ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L29/167 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200279931A1

公开(公告)日：2020-09-03

申请号：US16651294

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Dipanjan Basu ,  Sean T. Ma ,  Willy Rachmady ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.

公开(公告)号：US11362188B2

公开(公告)日：2022-06-14

申请号：US16651294

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Dipanjan Basu ,  Sean T. Ma ,  Willy Rachmady ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190341453A1

公开(公告)日：2019-11-07

申请号：US16465758

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Glenn A. Glass ,  Harold W. Kennel ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

公开(公告)号：US12191349B2

公开(公告)日：2025-01-07

申请号：US16649287

申请日：2017-12-15

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Cory E. Weber ,  Justin R. Weber ,  Sean T. Ma ,  Harold W. Kennel ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/201 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

公开(公告)号：US11575005B2

公开(公告)日：2023-02-07

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US11424335B2

公开(公告)日：2022-08-23

申请号：US16629555

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Dipanjan Basu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

公开(公告)号：US10930738B2

公开(公告)日：2021-02-23

申请号：US16611125

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78

Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.

公开(公告)号：US20200279910A1

公开(公告)日：2020-09-03

申请号：US16649287

申请日：2017-12-15

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Cory E. Weber ,  Justin R. Weber ,  Sean T. Ma ,  Harold W. Kennel ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/205 ,  H01L29/161 ,  H01L29/775

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

公开(公告)号：US20190305085A1

公开(公告)日：2019-10-03

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.