公开(公告)号：US20190297344A1

公开(公告)日：2019-09-26

申请号：US16440159

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/533 ,  H04N19/159 ,  H04N19/60 ,  H04N19/88 ,  H04N19/70 ,  H04N19/176

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US20190261001A1

公开(公告)日：2019-08-22

申请号：US16400882

申请日：2019-05-01

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC: H04N19/147 ,  H04N19/176 ,  H04N19/105 ,  H04N19/124 ,  H04N19/567

Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190037227A1

公开(公告)日：2019-01-31

申请号：US15663134

申请日：2017-07-28

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.

公开(公告)号：US11323700B2

公开(公告)日：2022-05-03

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12 ,  H04N19/60

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

公开(公告)号：US20210084294A1

公开(公告)日：2021-03-18

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

公开(公告)号：US10924753B2

公开(公告)日：2021-02-16

申请号：US14139716

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Atthar H. Mohammed ,  Srinivasan Embar Raghukrishnan

IPC: H04N19/436 ,  H04N19/577 ,  H04N19/573 ,  H04N19/53 ,  H04N19/58

Abstract: An apparatus may include a memory to receive an image frame to encode; and a modular motion estimation engine to process the image frame. The modular motion estimation engine includes modular motion estimation circuitry comprising a multiplicity of motion estimation circuits, and a motion estimation kernel for execution on the modular motion estimation circuitry to send the image frame through one or more configurable execution pipelines that each execute motion estimation over one or more of the motion estimation circuits.

公开(公告)号：US10855983B2

公开(公告)日：2020-12-01

申请号：US16440159

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12 ,  H04N19/60

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US10776897B1

公开(公告)日：2020-09-15

申请号：US16297129

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Ben J. Ashbaugh ,  Brandon Fliflet ,  Jeffery S. Boles ,  Srinivasan Embar Raghukrishnan ,  Rahul Kulkarni

IPC: G06T1/20 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a processor to configure a plurality of contexts of a command engine to execute a graphics workload comprising a plurality of walkers, allocate, from a pool of execution units of a graphics processor, a subset of execution units to each walker in the plurality of walkers based at least in part on the predetermined number of walkers configured for the context, for each context in the plurality of contexts, dispatch one or more walkers of the plurality of walkers to the execution units, and upon dispatch of the one or more walkers of the plurality of walkers, write an opcode to a computer-readable memory indicating that the dispatch of the walker is complete, wherein the opcode comprises dependency data for the one or more walkers of the plurality of walkers. Other embodiments may be described and claimed.

公开(公告)号：US10715818B2

公开(公告)日：2020-07-14

申请号：US15483146

申请日：2017-04-10

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Fangwen Fu ,  Satya N. Yedidi ,  Srinivasan Embar Raghukrishnan

IPC: H04N19/176 ,  H04N19/523 ,  H04N19/146 ,  H04N19/103 ,  H04N19/43

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit packing unit is to pack bits as coded according to the final macroblock coding decision into a data format.

公开(公告)号：US20190020872A1

公开(公告)日：2019-01-17

申请号：US15651620

申请日：2017-07-17

Applicant: Intel Corporation

Inventor： Fangwen Fu ,  Srinivasan Embar Raghukrishnan ,  Atthar H. Mohammed

IPC: H04N19/124 ,  H04N19/52 ,  H04N19/176

CPC classification number: H04N19/124 ,  G06F17/11 ,  H04N19/103 ,  H04N19/147 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Systems, apparatus and methods are described including operations for video coding rate control including Rate Distortion Optimized Quantization on a block-by-block basis.