公开(公告)号：US20240406380A1

公开(公告)日：2024-12-05

申请号：US18798562

申请日：2024-08-08

Applicant: Intel Corporation

Inventor： Qian Xu ,  Jian Hu ,  Navyasree Matturu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N19/105 ,  H04N19/176

Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.

公开(公告)号：US11423507B2

公开(公告)日：2022-08-23

申请号：US17159708

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Stanley J. Baran ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai R. Chan ,  Jill M. Boyce ,  Fangwen Fu ,  Satya N. Yedidi ,  Sumit Mohan ,  James M. Holland ,  Keith W. Rowe ,  Altug Koker

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/00 ,  H04N19/156 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3212

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：US10909653B2

公开(公告)日：2021-02-02

申请号：US16515794

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Stanley J. Baran ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai R. Chan ,  Jill M. Boyce ,  Fangwen Fu ,  Satya N. Yedidi ,  Sumit Mohan ,  James M. Holland ,  Keith W. Rowe ,  Altug Koker

IPC: G06T1/20 ,  H04N19/156 ,  G06T1/60 ,  G09G5/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3212

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：US20180300839A1

公开(公告)日：2018-10-18

申请号：US15488569

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Stanley J. Baran ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Jong Dae Oh ,  Hiu-Fai R. Chan ,  Jill M. Boyce ,  Fangwen Fu ,  Satya N. Yedidi ,  Sumit Mohan ,  James M. Holland ,  Keith W. Rowe ,  Altug Koker

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/00

CPC classification number: G06T1/20 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3265 ,  G06T1/60 ,  G06T2200/16 ,  G06T2210/52 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/0407 ,  H04N19/156 ,  Y02D10/153 ,  Y02D10/174

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.

公开(公告)号：US11025913B2

公开(公告)日：2021-06-01

申请号：US16400882

申请日：2019-05-01

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC: H04N19/176 ,  H04N19/147 ,  H04N19/567 ,  H04N19/124 ,  H04N19/105

Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190297344A1

公开(公告)日：2019-09-26

申请号：US16440159

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/533 ,  H04N19/159 ,  H04N19/60 ,  H04N19/88 ,  H04N19/70 ,  H04N19/176

Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.

公开(公告)号：US20190261001A1

公开(公告)日：2019-08-22

申请号：US16400882

申请日：2019-05-01

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi ,  Wenhao Zhang

IPC: H04N19/147 ,  H04N19/176 ,  H04N19/105 ,  H04N19/124 ,  H04N19/567

Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.

公开(公告)号：US20190037227A1

公开(公告)日：2019-01-31

申请号：US15663134

申请日：2017-07-28

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Lidong Xu ,  Fangwen Fu ,  Dmitry E. Ryzhov ,  Satya N. Yedidi

IPC: H04N19/43 ,  H04N19/53 ,  H04N19/567 ,  H04N19/115 ,  H04N19/61 ,  H04N19/126 ,  H04N19/96 ,  H04N19/192 ,  H04N19/557

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.

公开(公告)号：US11323700B2

公开(公告)日：2022-05-03

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12 ,  H04N19/60

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.

公开(公告)号：US20210084294A1

公开(公告)日：2021-03-18

申请号：US17107258

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James M. Holland ,  Srinivasan Embar Raghukrishnan ,  Zhijun Lei ,  Dmitry E. Ryzhov ,  Lidong Xu ,  Satya N. Yedidi

IPC: H04N19/11 ,  H04N19/533 ,  H04N19/159 ,  H04N19/176 ,  H04N19/88 ,  H04N19/70 ,  H04N19/593 ,  H04N19/33 ,  H04N19/12

Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.