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公开(公告)号：US20190304052A1
公开(公告)日：2019-10-03
申请号：US16441499
申请日：2019-06-14
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
IPC: G06T1/20 , G06T1/60 , G06F12/0888 , G06F12/0811 , G06F12/0815 , G06F12/0831
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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公开(公告)号：US20240394956A1
公开(公告)日：2024-11-28
申请号：US18675746
申请日：2024-05-28
Applicant: Intel Corporation
Inventor： Sven Woop , Michael J. Doyle , Sreenivas Kothandaraman , Karthik Vaidyanathan , Abhishek R. Appu , Carsten Benthin , Prasoonkumar Surti , Holger Gruen , Stephen Junkins , Adam Lake , Bret G. Alfieri , Gabor Liktor , Joshua Barczak , Won-Jong Lee
Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
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公开(公告)号：US11640297B2
公开(公告)日：2023-05-02
申请号：US17304153
申请日：2021-06-15
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Guei-Yuan Lueh , Supratim Pal , Ashutosh Garg , Chandra S. Gurram , Jorge E. Parra , Junjie Gu , Konrad Trifunovic , Hong Bin Liao , Mike B. MacPherson , Shubh B. Shah , Shubra Marwaha , Stephen Junkins , Timothy R. Bauer , Varghese George , Weiyu Chen
Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.
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公开(公告)号：US20230057492A1
公开(公告)日：2023-02-23
申请号：US17854310
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Sreenivas Kothandaraman , Stephen Junkins , Srihari Pratapa , Prasoonkumar Surti
Abstract: Interleaving of variable bitrate streams for GPU implementations is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a super-compression encoder pipeline to provide variable width interleaved coding; and memory for storage of data, wherein the graphics processor is to perform parallel dictionary encoding on a bitstream of symbols one of multiple workgroups, the workgroup to employ a plurality of encoders to generate a plurality of token-streams of variable lengths; create a histogram including at least tokens from the plurality of token-streams for the workgroup to generate an optimized entropy code; entropy code each of the plurality of token-streams for the workgroup into an encoded bitstream; and variably interleave the encoded bitstreams to generate an interleaved bitstream and bookkeep a size of the interleaved bitstream.
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Patent Agency Ranking
公开(公告)号：US20220301228A1
公开(公告)日：2022-09-22
申请号：US17357038
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Stephen Junkins , Sreenivas Kothandaraman , Prasoonkumar Surti , Srihari Pratapa , William Hux , John Feit
Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.
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公开(公告)号：US11042370B2
公开(公告)日：2021-06-22
申请号：US15957728
申请日：2018-04-19
Applicant: Intel Corporation
Inventor： Subramaniam Maiyuran , Guei-Yuan Lueh , Supratim Pal , Ashutosh Garg , Chandra S. Gurram , Jorge E. Parra , Junjie Gu , Konrad Trifunovic , Hong Bin Liao , Mike B. Macpherson , Shubh B. Shah , Shubra Marwaha , Stephen Junkins , Timothy R. Bauer , Varghese George , Weiyu Chen
Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.
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公开(公告)号：US10373285B2
公开(公告)日：2019-08-06
申请号：US15482810
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
IPC: G06T1/60 , G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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公开(公告)号：US20180293693A1
公开(公告)日：2018-10-11
申请号：US15482810
申请日：2017-04-09
Applicant: Intel Corporation
Inventor： Joydeep Ray , Altug Koker , James A. Valerio , David Puffer , Abhishek R. Appu , Stephen Junkins
CPC classification number: G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06F2212/1024 , G06F2212/302 , G06F2212/621 , G06F2212/656 , G06F2212/657 , G06T1/60
Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
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公开(公告)号：US08823720B2
公开(公告)日：2014-09-02
申请号：US13864512
申请日：2013-04-17
Applicant: Intel Corporation
Inventor： William A. Hux , Stephen Junkins
CPC classification number: G06T1/20 , G06T1/00 , G06T15/005
Abstract: Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.
Abstract translation: 方法，系统和数据结构产生一个光栅化器。 在机器结构上检测到图形状态。 图形状态用于组装外壳光栅化器。 机器架构用于选择替换外壳光栅化器中shell逻辑部分的替换逻辑。 机器架构用于将存储器管理逻辑选择性地插入到壳逻辑的部分以产生。
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