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公开(公告)号：US09852069B2
公开(公告)日：2017-12-26
申请号：US15357509
申请日：2016-11-21
Applicant: Intel Corporation
Inventor： James B. Crossland , Toby Opferman , Blaise Fanning
CPC classification number: G06F12/0638 , G06F12/023 , G06F12/0238 , G06F12/0866 , G06F2212/202 , G06F2212/2024 , G06F2212/205 , G11C7/1072 , G11C13/0004 , G11C14/0036 , G11C14/0045
Abstract: A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.
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公开(公告)号：US20170139827A1
公开(公告)日：2017-05-18
申请号：US15357509
申请日：2016-11-21
Applicant: Intel Corporation
Inventor： James B. Crossland , Toby Opferman , Blaise Fanning
CPC classification number: G06F12/0638 , G06F12/023 , G06F12/0238 , G06F12/0866 , G06F2212/202 , G06F2212/2024 , G06F2212/205 , G11C7/1072 , G11C13/0004 , G11C14/0036 , G11C14/0045
Abstract: A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.
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公开(公告)号：US09524227B2
公开(公告)日：2016-12-20
申请号：US14327375
申请日：2014-07-09
Applicant: Intel Corporation
Inventor： Toby Opferman , James B. Crossland , Jason W. Brandt , Beeman C. Strong
CPC classification number: G06F9/30123 , G06F9/30145 , G06F9/3877 , G06F11/3024 , G06F11/3079 , G06F11/3466 , G06F11/3471 , G06F11/348 , G06F11/36 , G06F11/3636 , G06F11/3656
Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.
Abstract translation: 描述用于产生抑制地址迹线的方法和装置。 在一些实施例中，处理器包括具有跟踪抑制器的跟踪发生器，该跟踪抑制器输出用于由处理器执行的指令的抑制地址跟踪。 在一些实施例中，用于为处理器生成抑制地址轨迹的方法包括从处理器的跟踪发生器的跟踪抑制器产生已执行指令的抑制地址轨迹。
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14.发明授权公开(公告)号：US11989129B2
公开(公告)日：2024-05-21
申请号：US16986490
申请日：2020-08-06
Applicant: Intel Corporation
Inventor： Kyle Delehanty , Sridharan Sakthivelu , Janardhana Yoga Narasimhaswamy , Vijay Bahirji , Toby Opferman
IPC: G06F12/0846 , G06F9/455 , G06F9/50 , G06F12/0806 , G06F12/0871
CPC classification number: G06F12/0851 , G06F9/45533 , G06F9/5016 , G06F12/0806 , G06F12/0871 , G06F2009/45583 , G06F2212/2542
Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.
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公开(公告)号：US20230091167A1
公开(公告)日：2023-03-23
申请号：US17482944
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Toby Opferman , Michael W. Chynoweth , Rajshree A. Chabukswar , Vijay C. Bahirji
Abstract: An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11409572B2
公开(公告)日：2022-08-09
申请号：US16586706
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Toby Opferman , Eliezer Weissmann , Robert Valentine , Russell Cameron Arnold
Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.
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公开(公告)号：US10733108B2
公开(公告)日：2020-08-04
申请号：US15980523
申请日：2018-05-15
Applicant: Intel Corporation
Inventor： Vijay Bahirji , Amin Firoozshahian , Mahesh Madhav , Toby Opferman , Omid Azizi
IPC: G06F12/00 , G06F12/1009 , G06F12/02
Abstract: A system for computer memory management that implements a memory pool table, the memory pool table including entries that describe a plurality of memory pools, each memory pool representing a group of memory pages related by common attributes; a per-page tracking table, each entry in the per-page tracking table used to related a memory page with a memory pool of the memory pool table; and processing circuitry to: scan each entry in the per-page tracking table and, for each entry: determine an amount of memory released if the memory page related with the entry is swapped; aggregate the amount of memory for the respective memory pool related with the memory page related with the entry in the per-page tracking table, to produce a per-pool memory aggregate; and output the per-pool memory aggregate for the memory pools related with the memory pages in the per-page tracking table.
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公开(公告)号：US10001953B2
公开(公告)日：2018-06-19
申请号：US15380266
申请日：2016-12-15
Applicant: Intel Corporation
Inventor： Leena K. Puthiyedath , Blaise Fanning , Toby Opferman , James B. Crossland
IPC: G06F3/00 , G06F3/06 , G06F12/00 , G06F12/0804
CPC classification number: G06F3/0679 , G06F3/061 , G06F3/0631 , G06F3/0643 , G06F3/0644 , G06F12/00 , G06F12/0238 , G06F12/0638 , G06F12/08 , G06F12/0804 , G06F12/0866 , G06F2212/1004 , G06F2212/1056 , G06F2212/2024 , G06F2212/214 , G06F2212/251 , G06F2212/7201
Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
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公开(公告)号：US20160378636A1
公开(公告)日：2016-12-29
申请号：US14751759
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Beeman C. Strong , Jason W. Brandt , Peter Lachner , Andreas Kleen , James B. Crossland , Toby Opferman
CPC classification number: G06F11/3466 , G06F11/3024 , G06F2201/865
Abstract: In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括一个核心，其核心是包括提取逻辑，以提取包括第一指令和第二指令的指令。 核心还包括执行指令的执行逻辑。 执行逻辑是响应于第二指令的执行，检索作为立即值，寄存器值和存储在存储单元中的存储器值之一的操作数值。 核心还包括输出包括响应于执行第二指令的操作数值的表示的数据包的逻辑。 核心还包括处理器跟踪（PT）逻辑以产生包括多个PT分组的处理器跟踪，其中每个PT分组对应于相应的第一指令的执行结果。 处理器跟踪逻辑进一步将数据包包含在处理器跟踪内。 描述和要求保护其他实施例。
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公开(公告)号：US20160092227A1
公开(公告)日：2016-03-31
申请号：US14962883
申请日：2015-12-08
Applicant: Intel Corporation
Inventor： Baiju V. Patel , James B. Crossland , Atul A. Khare , Toby Opferman
CPC classification number: G06F9/30145 , G06F9/30054 , G06F9/52 , G06F9/54 , G06F2209/521
Abstract: Robust system call and system return instructions are executed by a processor to transfer control between a requester and an operating system kernel. The processor includes execution circuitry and registers that store pointers to data structures in memory. The execution circuitry receives a system call instruction from a requester to transfer control from a first privilege level of the requester to a second privilege level of an operating system kernel. In response, the execution circuitry swaps the data structures that are pointed to by the registers between the requester and the operating system kernel in one atomic transition.
Abstract translation: 强大的系统调用和系统返回指令由处理器执行，以在请求者和操作系统内核之间传输控制。 处理器包括执行电路和寄存器，其存储指向存储器中的数据结构的指针。 执行电路从请求者接收系统调用指令，以将控制从请求者的第一特权级别转移到操作系统内核的第二特权级别。 作为响应，执行电路在一个原子转换中交换请求者和操作系统内核之间的寄存器所指向的数据结构。
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