公开(公告)号：US11322290B2

公开(公告)日：2022-05-03

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20200212020A1

公开(公告)日：2020-07-02

申请号：US16234302

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/528 ,  H01L23/498 ,  H01L21/56

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20200168536A1

公开(公告)日：2020-05-28

申请号：US16202690

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： Lauren Ashley Link ,  Andrew James Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Ying Wang ,  Chong Zhang

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/64

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

公开(公告)号：US20190206780A1

公开(公告)日：2019-07-04

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01F27/28 ,  H01L21/48 ,  H01F41/04 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US11830809B2

公开(公告)日：2023-11-28

申请号：US16829336

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ying Wang ,  Yikang Deng ,  Junnan Zhao ,  Andrew James Brown ,  Cheng Xu ,  Kaladhar Radhakrishnan

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L28/10

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

公开(公告)号：US20210111166A1

公开(公告)日：2021-04-15

申请号：US17129269

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US10692965B2

公开(公告)日：2020-06-23

申请号：US16142817

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Andrew J. Brown ,  Sheng Li ,  Sai Vadlamani ,  Ying Wang

IPC: H01L27/08 ,  H01L49/02 ,  H01F27/28 ,  C09D11/52 ,  H01L23/522 ,  G05F1/625

Abstract: Methods of forming an inductor using dry processes are described. A cavity is laser drilled in an insulator. A first magnetic material layer is printed in the cavity. An Ag conductive ink is printed on the first magnetic material layer and a second magnetic material layer printed on the ink. The ink has a trace sandwiched between the first and second magnetic material layers that provides a majority of the inductance of the inductor. A protective insulating layer protects the second magnetic material layer from a wet chemistry solution when contacts are formed to the ink. The second magnetic material layer and ink are deposited in or on the cavity.

公开(公告)号：US11894282B2

公开(公告)日：2024-02-06

申请号：US16446538

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Sergio Antonio Chan Arguedas ,  Peng Li ,  Chandra Mohan Jha ,  Aravindha R. Antoniswamy ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang

IPC: H01L23/367 ,  H01L23/433 ,  H01L23/498 ,  H01L23/053

CPC classification number: H01L23/3675 ,  H01L23/053 ,  H01L23/433 ,  H01L23/49816

Abstract: Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.

公开(公告)号：US11651885B2

公开(公告)日：2023-05-16

申请号：US16637006

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Junnan Zhao ,  Ying Wang ,  Cheng Xu ,  Kyu Oh Lee ,  Sheng Li ,  Yikang Deng

IPC: H01F17/00 ,  H01F27/255

CPC classification number: H01F17/0013 ,  H01F27/255 ,  H01F2017/002 ,  H01F2017/0066

Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.

公开(公告)号：US11557579B2

公开(公告)日：2023-01-17

申请号：US17129269

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Cheng Xu ,  Junnan Zhao ,  Ying Wang ,  Meizi Jiao

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.