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公开(公告)号：AU2008279973A1
公开(公告)日：2009-01-29
申请号：AU2008279973
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： YI HYO SEOK , PARK HYEONG GEUN , KO YOUNG JO , JEONG CHAN BOK , KIM YOUNG HOON , CHANG KAP SEOK , KIM IL GYU , BANG SEUNG CHAN
Abstract: The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
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公开(公告)号：AU2008279971A1
公开(公告)日：2009-01-29
申请号：AU2008279971
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： YI HYO SEOK , KIM YOUNG HOON , CHANG KAP SEOK , JEONG CHAN BOK , BANG SEUNG CHAN , PARK HYEONG GEUN , KO YOUNG JO , KIM IL GYU
Abstract: The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
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公开(公告)号：BRPI0810700A2
公开(公告)日：2015-10-13
申请号：BRPI0810700
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： JEONG CHAN BOK , YI HYO SEOK , PARK HYEONG GEUN , KIM IL GYU , CHANG KAP SEOK , BANG SEUNG CHAN , KIM YOUNG HOON , KO YOUNG JO
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公开(公告)号：BRPI0809496A2
公开(公告)日：2014-09-23
申请号：BRPI0809496
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
Abstract: The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
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15.发明专利
公开(公告)号：ES2380065T3
公开(公告)日：2012-05-08
申请号：ES10160271
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
Abstract: Un procedimiento de generación de una trama de enlace descendente (110) que incluye una señal de sincronización primaria y señales de sincronización secundarias, que comprende: generación de una primera secuencia corta y una segunda secuencia corta que indican la información de grupo de celdas; generación de una primera secuencia de aleatorización y una segunda secuencia de aleatorización determinadas por la señal de sincronización primaria; generación de una tercera secuencia de aleatorización determinada por un grupo de secuencias cortas -el sistema de comunicación inalámbrica usa una pluralidad de secuencias cortas y la pluralidad de secuencias cortas están agrupadas en una pluralidad de grupos de secuencia corta- a la que se asigna la primera secuencia corta y una cuarta secuencia de aleatorización determinada por un grupo de secuencias cortas al que se asigna la segunda secuencia corta; aleatorización de la primera secuencia corta con la primera secuencia de aleatorización y aleatorización de la segunda secuencia corta con la segunda secuencia de aleatorización y la tercera secuencia de aleatorización; aleatorización de la segunda secuencia corta con la primera secuencia de aleatorización y aleatorización de la primera secuencia corta con la segunda secuencia de aleatorización y la cuarta secuencia de aleatorización; y correspondencia de la señal de sincronización secundaria que incluye la primera secuencia corta aleatorizada con la primera secuencia de aleatorización, la segunda secuencia corta aleatorizada con la segunda secuencia de aleatorización y la tercera secuencia de aleatorización, la segunda secuencia corta aleatorizada con la primera secuencia de aleatorización y la primera secuencia corta aleatorizada con la segunda secuencia de aleatorización y la cuarta secuencia de aleatorización a un dominio de frecuencias.
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Patent Agency Ranking16.发明专利
公开(公告)号：ES2356030T3
公开(公告)日：2011-04-04
申请号：ES08778879
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
Abstract: Un procedimiento de generación de una trama de enlace descendente (110) que incluye una señal de sincronización primaria y una señal de sincronización secundaria en un sistema de comunicación inalámbrica que comprende: generar una primera secuencia corta y una segunda secuencia corta que indican información del grupo de celdas; generar una primera secuencia de cifrado y una segunda secuencia de cifrado determinadas por la señal de sincronización primaria; generar una tercera secuencia de cifrado determinada por un grupo de secuencias cortas el sistema de comunicación inalámbrica usa una pluralidad de secuencias cortas y la pluralidad de secuencias cortas está agrupada en una pluralidad de grupos de secuencias cortas al que está asignado la primera secuencia corta; cifrar la primera secuencia corta con la primera secuencia de cifrado y cifrar la segunda secuencia corta con la segunda secuencia de cifrado y la tercera secuencia de cifrado; y modular la señal de sincronización secundaria que incluye la primera secuencia corta cifrada y la 15 segunda secuencia corta cifrada a un dominio de la frecuencia.
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公开(公告)号：DE602008003768D1
公开(公告)日：2011-01-13
申请号：DE602008003768
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
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公开(公告)号：KR20120014753A
公开(公告)日：2012-02-20
申请号：KR20100076918
申请日：2010-08-10
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： HWANG SOO YUN , PARK GI YOON , CHUNG HEE SANG , KIM HYUNG JIN , JEONG CHAN BOK , BAE HYOUNG OH , KIM DAE HO
IPC: H03M13/09
CPC classification number: H03M13/091 , H03M13/6561
Abstract: PURPOSE: An apparatus for generating a cyclic redundancy check code is provided to reduce processing time for generating a cyclic redundancy check code by increasing the number of a data bit which is processed at one clock cycle through parallel processing. CONSTITUTION: A CRC code generator(100) includes a serial/parallel convertor(110), adders(121-128,171-178,181-188), and selectors(131-138). The CRC code generator includes the parallel-serial converter(140), masking arithmetic units(151-156), and shift register lines(161-163). The serial/parallel convertor parallely transforms inputted data into eight data. Each of adders performs an OR operation feedback data outputted in a final shift register line and data outputted in the serial/parallel convertor. Shift register lines respectively include eight shift registers which are formed in parallel.
Abstract translation: 目的：提供一种用于生成循环冗余校验码的装置，以通过增加通过并行处理在一个时钟周期处理的数据比特数来减少用于生成循环冗余校验码的处理时间。 构成：CRC码发生器（100）包括串行/并行转换器（110），加法器（121-128,171-178,181-188）和选择器（131-138）。 CRC码发生器包括并行 - 串行转换器（140），屏蔽运算单元（151-156）和移位寄存器线（161-163）。 串行/并行转换器将输入的数据并行转换为八个数据。 每个加法器执行在最终移位寄存器行中输出的或运算反馈数据和串行/并行转换器中输出的数据。 移位寄存器线分别包括并行形成的八个移位寄存器。
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公开(公告)号：EP2137872A4
公开(公告)日：2010-03-03
申请号：EP08778879
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
CPC classification number: H04W48/16 , H04B1/70735 , H04B7/2656 , H04J11/0069 , H04L7/043 , H04L27/2613 , H04L27/2655 , H04W56/00 , H04W72/042 , H04W72/0446 , H04W88/08
Abstract: The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
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公开(公告)号：EP2127189A4
公开(公告)日：2010-03-17
申请号：EP08778878
申请日：2008-07-18
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： CHANG KAP SEOK , KIM IL GYU , PARK HYEONG GEUN , KO YOUNG JO , YI HYO SEOK , JEONG CHAN BOK , KIM YOUNG HOON , BANG SEUNG CHAN
CPC classification number: H04W48/16 , H04B1/70735 , H04B7/2656 , H04J11/0069 , H04L7/043 , H04L27/2613 , H04L27/2655 , H04W56/00 , H04W72/042 , H04W72/0446 , H04W88/08
Abstract: The present invention proposes a method of generating a downlink frame including a primary synchronization signal and secondary synchronization signals with which interference between sectors can be reduced so as to improve the performance for searching cells. The method comprises the steps of generating a first short sequence and a second short sequence, generating a first scrambling sequence and a second scrambling sequence by the primary synchronization signal, generating a third scrambling sequence determined by a short sequence group to which the first short sequence is assigned and a fourth scrambling sequence determined by a short sequence group to which the second short sequence is assigned, scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence, scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence, and mapping the secondary synchronization signal that including the scambled short sequences and the fourth to a frequency domain.
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