公开(公告)号：KR20120014753A

公开(公告)日：2012-02-20

申请号：KR20100076918

申请日：2010-08-10

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： HWANG SOO YUN ,  PARK GI YOON ,  CHUNG HEE SANG ,  KIM HYUNG JIN ,  JEONG CHAN BOK ,  BAE HYOUNG OH ,  KIM DAE HO

IPC: H03M13/09

CPC classification number: H03M13/091 ,  H03M13/6561

Abstract: PURPOSE: An apparatus for generating a cyclic redundancy check code is provided to reduce processing time for generating a cyclic redundancy check code by increasing the number of a data bit which is processed at one clock cycle through parallel processing. CONSTITUTION: A CRC code generator(100) includes a serial/parallel convertor(110), adders(121-128,171-178,181-188), and selectors(131-138). The CRC code generator includes the parallel-serial converter(140), masking arithmetic units(151-156), and shift register lines(161-163). The serial/parallel convertor parallely transforms inputted data into eight data. Each of adders performs an OR operation feedback data outputted in a final shift register line and data outputted in the serial/parallel convertor. Shift register lines respectively include eight shift registers which are formed in parallel.

Abstract translation: 目的：提供一种用于生成循环冗余校验码的装置，以通过增加通过并行处理在一个时钟周期处理的数据比特数来减少用于生成循环冗余校验码的处理时间。 构成：CRC码发生器（100）包括串行/并行转换器（110），加法器（121-128,171-178,181-188）和选择器（131-138）。 CRC码发生器包括并行 - 串行转换器（140），屏蔽运算单元（151-156）和移位寄存器线（161-163）。 串行/并行转换器将输入的数据并行转换为八个数据。 每个加法器执行在最终移位寄存器行中输出的或运算反馈数据和串行/并行转换器中输出的数据。 移位寄存器线分别包括并行形成的八个移位寄存器。

公开(公告)号：KR20120027826A

公开(公告)日：2012-03-22

申请号：KR20100089619

申请日：2010-09-13

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM EUN TAE ,  CHO DAE SOON ,  CHUNG HEE SANG ,  BAE JUNG SOOK ,  KIM DAE HO

IPC: H03M13/09 ,  H03M13/27

CPC classification number: H04L1/0067 ,  H03M13/3723 ,  H03M13/653 ,  H04L1/0072

Abstract: PURPOSE: An apparatus for decoding a control channel in a wireless telecommunication system is provided to improve data processing performance in a wireless telecommunication system by improving the integration degree of the wireless telecommunication system. CONSTITUTION: A candidate data extracting unit(210) extracts candidate data from demodulated data. A derate matching unit(220) performs derate matching and sub-block interleaving about the candidate data. A data validity determining unit(230) determines tail biting viterbi decoding for the candidate data offered from the derate matching unit. A tail biting viterbi decoding unit(240) performs the tail biting Viterbi decoding for derate matching data. A CRC(Cyclic Redundancy Check) checking unit(250) performs a CRC test for tail biting viterbi decoded data. A DCI(Downlink Control Information) detection determining unit(260) determines the detection of DCI from the candidate data.

Abstract translation: 目的：提供一种用于解码无线电信系统中的控制信道的装置，通过提高无线电信系统的集成度来提高无线电信系统中的数据处理性能。 构成：候选数据提取单元（210）从解调数据中提取候选数据。 降级匹配单元（220）对候选数据执行降级匹配和子块交织。 数据有效性确定单元（230）为从降额比较单元提供的候选数据确定尾巴维特比解码。 尾部维特比解码单元（240）执行用于降额匹配数据的尾部维特比解码。 CRC（循环冗余校验）检查单元（250）对尾部维特比解码数据执行CRC测试。 DCI（下行链路控制信息）检测确定单元（260）根据候选数据确定DCI的检测。

公开(公告)号：KR20120003184A

公开(公告)日：2012-01-10

申请号：KR20100063901

申请日：2010-07-02

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： HWANG HYUN GU ,  LEE JAE KYUNG ,  JANG JAE DEUG ,  JEONG KIL SOO ,  KIM DAE HO

IPC: H04W56/00

CPC classification number: H04W56/004

Abstract: PURPOSE: A time synchronization communicating system is provided to effectively control time synchronization by determining the reacquisition of time synchronization according to signal qualities. CONSTITUTION: The information of an interesting signal is acquired(S110). The time synchronization of the interesting signal is traced by using the acquired information(S120). The synchronization breakaway of a time synchronization tracking is determined according to the quality of the interesting signal and last movement rates of time synchronization(S130). In case the synchronization is breakaway, the reacquisition of the time synchronization is determined according to the quality of the interesting signal(S140).

Abstract translation: 目的：提供时间同步通信系统，通过根据信号质量确定时间同步的重新获取，有效地控制时间同步。 构成：获取有趣信号的信息（S110）。 通过使用所获取的信息来跟踪感兴趣信号的时间同步（S120）。 根据感兴趣信号的质量和时间同步的最后移动速率来确定时间同步跟踪的同步分离（S130）。 在同步分离的情况下，根据感兴趣信号的质量来确定时间同步的重新获取（S140）。

公开(公告)号：KR20120070811A

公开(公告)日：2012-07-02

申请号：KR20100132278

申请日：2010-12-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM EUN TAE ,  CHUNG HEE SANG ,  KIM DAE HO

IPC: H03M13/09

CPC classification number: H03M13/09 ,  H03M13/3746 ,  H03M13/413 ,  H03M13/6597

Abstract: PURPOSE: A decoder and a method for eliminating error data are provided to ensure system stability by preventing performance degradation caused by error data. CONSTITUTION: A candidate data extracting unit(110) receives data demodulated through a demodulator. A de-rate matching unit(120) performs de-rate matching for candidate data. A channel decoding unit(130) performs channel decoding for de-rate matched data. A state matching determining unit(140) compares an initial state metric with a final state metric in survivor path information. A reference accumulation path determining unit(150) determines the survivor path information to satisfy a reference accumulation path value. A cyclic redundancy checking unit(160) performs cyclic redundancy check for inputted candidate data. An accumulation path queue determining unit(170) aligns all down link control information data determined as valid data through the cyclic redundancy check based on the survivor path information.

Abstract translation: 目的：提供解码器和消除错误数据的方法，以通过防止错误数据引起的性能下降来保证系统的稳定性。 构成：候选数据提取单元（110）接收通过解调器解调的数据。 解速率匹配单元（120）对候选数据执行解速率匹配。 信道解码单元（130）对去速率匹配数据进行信道解码。 状态匹配确定单元（140）将初始状态度量与幸存路径信息中的最终状态度量进行比较。 参考累积路径确定单元（150）确定幸存者路径信息以满足参考累积路径值。 循环冗余校验单元（160）对输入的候补数据进行循环冗余校验。 累积路径队列确定单元（170）通过基于幸存路径信息的循环冗余校验来对齐被确定为有效数据的所有下行链路控制信息数据。