公开(公告)号：GB2296374B

公开(公告)日：1999-03-24

申请号：GB9425589

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/33

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：GB2312095B

公开(公告)日：1997-12-17

申请号：GB9710128

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO KEOK-HO ,  KANG JIN-YOUNG

IPC: H01L21/762 ,  H01L21/3105

公开(公告)号：DE4444776A1

公开(公告)日：1996-06-27

申请号：DE4444776

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L29/735

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：GB2296129B

公开(公告)日：1998-06-24

申请号：GB9425342

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：GB2295487B

公开(公告)日：1997-12-03

申请号：GB9425223

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  KANG JIN-YOUNG

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

公开(公告)号：DE4445344A1

公开(公告)日：1996-06-27

申请号：DE4445344

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76 ,  H01L29/73 ,  H01L27/12 ,  H01L21/20 ,  H01L21/84

Abstract: A method of fabricating a Silicon On Insulator (SOI) substrate for a bipolar transistor is described comprising the steps of forming a first insulating layer (23a) on a single crystal silicon substrate (21); patterning the first insulating layer to form an opening; growing a single crystal silicon layer (31) in the opening to form active and inactive regions; polishing the active region (31) with the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer (23b) on the planarized surface; bonding a bonding substrate (27) to the second insulating layer; and polishing the silicon substrate using the first insulating layer (23a) as a stopper up to a surface of the active region. By this method, the stray capacitance occurring between the SOI substrate and any metal wiring portion formed thereon can be significantly reduced owing to the relatively thick insulating layer therebetween, and the parasitic capacitance can be substantially eliminated due to the insulating layer interposed between the bonding substrate and the active region that is to be used as a buried collector.

公开(公告)号：GB2296374A

公开(公告)日：1996-06-26

申请号：GB9425589

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/33

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：GB2296129A

公开(公告)日：1996-06-19

申请号：GB9425342

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737

Abstract: Fabrication of a bipolar transistor with a super self-aligned vertical structure of which the emitter 34, the base 32 and the collector 31 are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region 22 in a silicon substrate 21 by using ion-implementation of an impurity and thermal-annealing; sequentially forming several layers 23 to 28; selectively removing the nitride and polysilicon layers 27, 28 to form a pattern; sequentially forming a silicon oxide layer 29, a nitride layer (17, Fig. 3a) and a silicon oxide layer (18) theron; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall (19, Fig. 3b) on both sides of the opening; forming a collector 31 on a surface portion of the buried collector region 22 up to a lower surface of the polysilicon layer 28; removing the side wall (19) and the third nitride layer (17) to expose a side surface of the second polysilicon layer 28; selectively forming a base 32 on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer 33 on both sides of the base and the silicon oxide to define an emitter region; forming an emitter 34 on the base 32 and forming electrodes 36 thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.