公开(公告)号：GB2296375B

公开(公告)日：1998-06-24

申请号：GB9425590

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  KWON OH-JOON

IPC: H01L21/331 ,  H01L29/737

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 ANGSTROM thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.

公开(公告)号：GB2296376A

公开(公告)日：1996-06-26

申请号：GB9425603

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  CHO DEOK-HO ,  LEE SOO-MIN ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76

Abstract: A bipolar transistor has a buried collector 22 on a silicon substrate 21, a collector 23 defined by trenches filled with insulating material, an intrinsic base 30 formed on the collector 23, an extrinsic base 26 electrically isolated from the silicon substrate 21 by a thermal-oxide layer 25, a conductive polysilicon layer 31 formed in self-alignment to connect the intrinsic base with the extrinsic base, and an emitter 33 formed on a portion of the intrinsic base and composed of polysilicon doped with an impurity. The trench may be defined by etching, or by a side-wall nitride layer.

公开(公告)号：DE4444609A1

公开(公告)日：1996-05-30

申请号：DE4444609

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  KANG JIN-YOUNG

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

Abstract: The method comprises the steps of forming a trench in a substrate 51 to separate an active region from an inactive region, filling the trench with an oxidisation blocking material 59, capping the active region to prevent oxidisation thereof and oxidising to form a field oxide film 50 in the inactive region. No oxygen penetrates into the active region during the oxidation whereby a field oxide film can be formed without occurrence of a bird's beak. This enables fabrication of the semiconductor devices required for the production of memories of 1Gb or more. Two distinct methods are disclosed with reference to Figs 5a to 5j and 6a to 6h respectively. In the first, inactive and active regions are first formed using a photomask and the trench is subsequently formed. The oxidisation blocking material is then formed to fill the trench and cover the sidewall of the active region. In the second, inactive and active regions are defined by using a trench mask. The oxidisation blocking material is then formed to fill the trench and cover the inactive and active regions after which it is removed from these regions by polishing.

公开(公告)号：DE4445345A1

公开(公告)日：1996-06-27

申请号：DE4445345

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  CHO DEOK-HO ,  LEE SOO-MIN ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

公开(公告)号：GB2296376B

公开(公告)日：1997-07-09

申请号：GB9425603

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  CHO DEOK-HO ,  LEE SOO-MIN ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

公开(公告)号：DE19643903A1

公开(公告)日：1997-06-26

申请号：DE19643903

申请日：1996-10-30

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  CHO DEOK-HO ,  LEE SOO-MIN ,  PYUN KWANG-EUI

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: The method initially involves forming a buried collector (2), collector thin film (3), and collector sink on a semiconductor substrate. On the collector structure are formed a silicon oxide film (8), a polysilicon film (9) for a base electrode, a nitride film, and an oxide film. The silicon oxide film is photolithographically exposed and an insulating spacing layer formed on the exposed region side, thus limiting an active region. Then the collector thin film is exposed, using the existing structure as a mask, and a lateral auxiliary film formed for component separation. An ion implantation of a dopant forms a selective collector region (10) in the active region. Then the auxiliary film is removed, the exposed part etched, and a separating, flat trough (17) is formed. Then a side polysilicon film (18) and a self aligning base are formed. A heat treatment after th formation of the collector sink follows which provides an oxide film on its upper section and activates dopants within the collector sink.

公开(公告)号：DE4445344C2

公开(公告)日：1996-10-02

申请号：DE4445344

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76 ,  H01L29/73 ,  H01L27/12 ,  H01L21/20 ,  H01L21/84

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：GB2296374B

公开(公告)日：1999-03-24

申请号：GB9425589

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/33

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

公开(公告)号：DE19650493A1

公开(公告)日：1997-06-26

申请号：DE19650493

申请日：1996-12-05

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  PYUN KWANG-EUI

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/73 ,  H01L21/76

Abstract: The transistor includes a semiconductor substrate, e.g. of silicon, with a buried collector and having an oxide film with a conductive, thin-film base electrode formed on the substrate one after another. The substrate is provided with a heterojunction of e.g. Si or SiGe Ge. The collector is surrounded by the conductive thin film and is formed in transistor active region, bounded by patterns of the conductive thin and first oxide films on the buried collector on both sides of the conductive thin film is formed a first spacing layer. A multilayer base is formed in the active region, while an emitter is grown selectively on the base in an emitter region, bounded by etching of a second oxide film, on whose both sides is formed a second spacing layer. The emitter carries an electrode, while a passivating insulation layer is formed on the structure surface. Metal coupling lines are formed on the base, emitter, and buried collector and go back through the insulation passivation layer and/or the two oxide layers.

公开(公告)号：DE4444776A1

公开(公告)日：1996-06-27

申请号：DE4444776

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L29/735

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.