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公开(公告)号：GB2261093A
公开(公告)日：1993-05-05
申请号：GB9213382
申请日：1992-06-24
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: MOS circuit 1 yields a high-impedance output current i proportional to the product of Vg and the symmetrical input Vx, - Vx. M1 operates in the triode region with symmetrical source and drain potentials ensured by matched loads M4, M5. M2 mirrors the input leg current to the output node A, and PMOS M3 cancels the offset current due to finite V1 of M1. Load Z provides a voltage output, with optional M8 acting as a synapse. Input switches may be inserted (fig. 5).
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公开(公告)号：PT100692B
公开(公告)日：1999-06-30
申请号：PT10069292
申请日：1992-07-15
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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公开(公告)号：GB2317980A
公开(公告)日：1998-04-08
申请号：GB9720798
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A multiplier capable of removing nonlinear current uses current mirror circuits. The multiplier uses MOSFET and BJT devices made by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q 3 and a BJT Q 5 , the BJT Q 3 being coupled in series to the n-channel MOSFET M1 between voltage V 1 and a ground voltage level. A second current mirror includes a BJT Q 4 and a BJT Q 6 . Consequently, input voltage signals V 1 and V dc applied to the n-channel MOSFET M1 determine the current I 1 and input voltage signals V 1 and V 2 applied to the n-channel MOSFET M2 determine the current I 2 .
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公开(公告)号：GB2261092A
公开(公告)日：1993-05-05
申请号：GB9213381
申请日：1992-06-24
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A MOSFET analog multiplier has a variable resistive MOSFET linear means (20) for linearly varying output current I depending upon a symmetrical input voltage from voltage sources (V2 and -V2) and an input voltage from an input voltage source (V1) and an operational amplifying unit (10) which includes an operational amplifier (U) and a feedback element (Z).
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公开(公告)号：DK81692A
公开(公告)日：1993-05-02
申请号：DK81692
申请日：1992-06-19
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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Patent Agency Ranking
公开(公告)号：LU88147A1
公开(公告)日：1993-02-15
申请号：LU88147
申请日：1992-07-15
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
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公开(公告)号：FR2754083B1
公开(公告)日：1999-06-18
申请号：FR9712220
申请日：1997-10-01
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q3 and a BJT Q5 and also the BJT Q3 is coupled in series to the n-channel MOSFET M1 between the voltage V1 and a ground voltage level. A second current mirror includes a BJT Q7 and a BJT Q8. A third current mirror includes a BJT Q4 and a BJT Q6. Consequently, input voltage signals V1 and Vdc applied to the n-channel MOSFETs M1 determine the current I1 and input voltage signals V1 and V2 applied to the n-channel MOSFET M2 determine the current I2.
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公开(公告)号：GB2319127A
公开(公告)日：1998-05-13
申请号：GB9720799
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIM DAE HWAN
Abstract: Apparatus for converting a voltage into pulses has a charging part 11 receiving the voltage, a voltage comparing part 12 for comparing the output voltage from the charging part 11 with a reference voltage value, a pulse extracting part 13 for outputting pulses in response to the comparison result; and a discharging part 14 for discharging the charge in the charging part 11 in response to the output signal of the pulse extracting part 13 or the comparing part 12.
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公开(公告)号：GB2317726A
公开(公告)日：1998-04-01
申请号：GB9720800
申请日：1997-09-30
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG , CHOI YOUNG JAE , KIM DAE HWAN
Abstract: A multiplier and a neural network synapse capable of removing nonlinear current use current mirror circuits The multiplier produces a linear current by using MOS transistors operating in the nonsaturation region. The multiplier comprises a first current mirror M1, M3, M7 to form a first current I 1 and a second current mirror M2, M4, M5 to form a second current I 2 , wherein the second current mirror is coupled in parallel to the first current mirror. The multiplier outputs an output current by subtracting the second current from first current, the output current representing the result of multiplying input voltages V 1 and V 2 . In a neural network synapse the input voltage V 1 is constant and the input voltage V 2 represents the synapse weight. An additional MOS transistor transfers the output current to the load in response to a neural state pulse.
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公开(公告)号：CH684665A5
公开(公告)日：1994-11-15
申请号：CH224192
申请日：1992-07-16
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
IPC: G06G7/163 , G06N3/063 , H03F3/16 , H01L29/784
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