公开(公告)号：FR2769430B1

公开(公告)日：1999-12-10

申请号：FR9712437

申请日：1997-10-06

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: H03K7/08 ,  H03K3/02 ,  H03K5/24

公开(公告)号：FR2769388A1

公开(公告)日：1999-04-09

申请号：FR9712488

申请日：1997-10-07

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06G7/164 ,  G06N3/063 ,  G06F15/80 ,  G06G7/60

Abstract: The multiplier includes a first current mirror (M1, M3, and M7) which forms a first current l1. A second current mirror (M2, M4, and M5) forms a second current l2. The second current mirror is coupled in parallel to the first mirror. The multiplier outputs an output current by subtracting the second current from the first current. The output current represents the result of multiplying input voltages V1 and V2.

公开(公告)号：GB2319127B

公开(公告)日：2000-09-06

申请号：GB9720799

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06F3/05 ,  H03K21/00 ,  H03M1/54 ,  H03M1/60

Abstract: Apparatus for converting a voltage into pulses has a charging part 11 receiving the voltage, a voltage comparing part 12 for comparing the output voltage from the charging part 11 with a reference voltage value, a pulse extracting part 13 for outputting pulses in response to the comparison result; and a discharging part 14 for discharging the charge in the charging part 11 in response to the output signal of the pulse extracting part 13 or the comparing part 12.

公开(公告)号：GB2317726B

公开(公告)日：2000-08-16

申请号：GB9720800

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06G7/14 ,  G06F7/44 ,  G06G7/163 ,  G06G7/60 ,  G06N3/063

Abstract: A multiplier and a neural network synapse capable of removing nonlinear current using current mirror circuits. The multiplier produces a linear current by using MOS transistors operating in a nonsaturation region. The multiplier includes a first current mirror including a plurality of MOS transistors to form a first current and a second current mirror including a plurality of MOS transistors to form a second current, wherein the second current mirror is coupled in parallel to the first current mirror. As a result, the multiplier outputs an output current by subtracting a second current from said first current.

公开(公告)号：FR2769430A1

公开(公告)日：1999-04-09

申请号：FR9712437

申请日：1997-10-06

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: H03K7/08 ,  H03K3/02 ,  H03K5/24

Abstract: The apparatus has a charging device that charges a current inputted from outside. A voltage comparing device compares the output voltage from the charging device with a reference voltage value and outputs a comparison result. A pulse extracting device generates and outputs pulses in response to the comparison result. A discharging device discharges the current through the charger in response to the output signal of the pulse extractor.

公开(公告)号：GB2319127A

公开(公告)日：1998-05-13

申请号：GB9720799

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06F3/05 ,  H03K21/00 ,  H03M1/54 ,  H03M1/60

Abstract: Apparatus for converting a voltage into pulses has a charging part 11 receiving the voltage, a voltage comparing part 12 for comparing the output voltage from the charging part 11 with a reference voltage value, a pulse extracting part 13 for outputting pulses in response to the comparison result; and a discharging part 14 for discharging the charge in the charging part 11 in response to the output signal of the pulse extracting part 13 or the comparing part 12.

公开(公告)号：GB2317726A

公开(公告)日：1998-04-01

申请号：GB9720800

申请日：1997-09-30

Applicant: KOREA TELECOMMUNICATION

Inventor： HAN IL SONG ,  CHOI YOUNG JAE ,  KIM DAE HWAN

IPC: G06G7/14 ,  G06F7/44 ,  G06G7/163 ,  G06G7/60 ,  G06N3/063 ,  G06F15/18

Abstract: A multiplier and a neural network synapse capable of removing nonlinear current use current mirror circuits The multiplier produces a linear current by using MOS transistors operating in the nonsaturation region. The multiplier comprises a first current mirror M1, M3, M7 to form a first current I 1 and a second current mirror M2, M4, M5 to form a second current I 2 , wherein the second current mirror is coupled in parallel to the first current mirror. The multiplier outputs an output current by subtracting the second current from first current, the output current representing the result of multiplying input voltages V 1 and V 2 . In a neural network synapse the input voltage V 1 is constant and the input voltage V 2 represents the synapse weight. An additional MOS transistor transfers the output current to the load in response to a neural state pulse.