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    11.
    发明专利
    未知

    公开(公告)号：DE60032051D1

    公开(公告)日：2007-01-11

    申请号：DE60032051

    申请日：2000-04-18

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHITTIPEDDI SAILESH ,  KELLY MICHAEL J

    IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

    Abstract: First and second trenches of differing depths are formed in a first insulating layer (12), a second insulating layer and polysilicon material then being formed. Part of the polysilicon is removed and an implantation barrier (40) is formed. Forming a multilayer semiconductor structure (50) comprises: (i) forming two trenches of different depths in the first insulating layer (12); (ii) forming the second insulating layer in the trenches; (iii) forming polysilicon material in the trenches so they are substantially filled; (iv) removing a portion of the polysilicon so the top surface (18) of the first insulating layer is not coplanar with a top surface of the polysilicon remaining in the trenches; (v) forming an implantation barrier (40) in the trenches; and (vi) processing the implantation barrier in the trenches so its top surface (42) is coplanar with the top surface of the first insulating layer. An independent claim is also included for: the multilayered semiconductor structure comprising the layers described on a substrate.

    Wire bonding method for semiconductor devices
    13.
    发明专利
    Wire bonding method for semiconductor devices 未知

    公开(公告)号：GB2362510A

    公开(公告)日：2001-11-21

    申请号：GB0030013

    申请日：2000-12-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

    IPC: H01L21/60 ,  H01L21/607 ,  H01L23/485 ,  H01L23/482

    Abstract: The present invention uses wire bonding technology to bond pads of interconnect materials 31 such as copper that oxidize easily using a wire made of Al, an Al alloy or an Al-coated gold wire 30. A passivation layer 32 of Ta is formed on the semiconductor substrate to encapsulate the bonding pad 31 made from the interconnect material such that the wire 30 bonds with the passivation layer itself, not with the interconnect material. The Ta layer 32 is metallurgically stable when bonded to the interconnect material and forms tantalum aluminide with the wire 30. Since the wire is stable compared with the interconnect material, i.e ., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device and the wire.

    Wire bonding method for copper interconnects in semiconductor devices
    14.
    发明专利
    Wire bonding method for copper interconnects in semiconductor devices 未知

    公开(公告)号：GB2362510B

    公开(公告)日：2003-07-02

    申请号：GB0030013

    申请日：2000-12-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

    IPC: H01L21/60 ,  H01L21/607 ,  H01L23/485 ,  H01L23/482

    Abstract: The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.

    16.
    发明专利
    未知

    公开(公告)号：DE60039800D1

    公开(公告)日：2008-09-25

    申请号：DE60039800

    申请日：2000-01-13

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

    IPC: H01L21/60 ,  H01L21/603 ,  H01L23/485

    Abstract: The specification describes techniques for wire bonding gold wires (78) to copper metallization (44) in semiconductor integrated circuits. A barrier layer (73) is formed on the copper, and an aluminum bonding pad (77) is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.

    Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer
    18.
    发明专利
    Process for manufacturing a dual damascene structure for an integrated circuit using an etch stop layer 未知

    公开(公告)号：GB2356974A

    公开(公告)日：2001-06-06

    申请号：GB0019489

    申请日：2000-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

    IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: A process for manufacturing a dual damascene structure for an integrated circuit involves forming a first opening (135) in a stack of layers including a first layer (105), second layer (115) and an etch stop layer (110), and forming a second opening (125) smaller than the first opening (135). The second opening (125) is formed in a portion of the base of the first opening (135). Preferably the first opening (135) is formed before the second opening (125). The etch stop layer (110) may be a hardmask, and the first (105) and second (115) layers may be dielectrics. The two openings may be filled with conductive material (145) to create vias and interconnects for an integrated circuit. Patterned masks (120, 130) may be used to produce the dual damascene structure, where the mask used to create the second opening (130) is deposited over the mask used to create the first opening (120).

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