公开(公告)号：JP2000036510A

公开(公告)日：2000-02-02

申请号：JP12334299

申请日：1999-04-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  RYAN VIVIAN WANDA

IPC: H01L27/04 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To provide a bond pad supporting structural body to be used for an integrated circuit having a bond pad positioned on this. SOLUTION: A bond pad supporting structural body 300 is positioned under a bond pad, provided with a supporting layer having plural openings 310-360 formed inside, and positioned on a dielectric layer. Also, the dielectric layer extended at least partially in the openings 310-360 is included for forming a bond pad supporting face in at least one part of the openings. One part of the openings 310-360 of the bond pad supporting structure 300 is filled with the dielectric layer being the second bond pad supporting layer in this unique structural body. Thus, it is possible to form an inclined synthetic supporting structural body acting as a differential force transducer, in response to an inside stress and a bonding stress in the integrated circuit according to the cooperation of the structural bodies of those two layers.

公开(公告)号：JP2001189343A

公开(公告)日：2001-07-10

申请号：JP2000386402

申请日：2000-12-20

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device provided with an interconnected structure made of copper. SOLUTION: A passivation layer 32 is formed on a semiconductor substrate. Material for the layer 32 is selected from among materials (such as Ta material), which are metallurgicolly stable, when the materials are bonded to an interconnecting material. The layer 32 is formed between interconnecting parts 31 and a wire 30. This layer 32 makes direct contacting with the wire 30 made of Al with the interconnecting parts 31 made of Cu avoided.

公开(公告)号：JP2000216191A

公开(公告)日：2000-08-04

申请号：JP2000007951

申请日：2000-01-17

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH M

IPC: H01L21/60 ,  H01L21/603 ,  H01L23/485

Abstract: PROBLEM TO BE SOLVED: To form a barrier layer on a copper, to form an aluminum pad on the barrier, and then to bond a gold wire to a copper metallized layer on the aluminum pad. SOLUTION: A cap layer 72 is formed on a silicon board 11, and a window is provided to expose a copper metallized layer in the cap layer 72. The barrier 73 and an aluminum layer 74 are blanket-deposited on the cap layer 72 and also in the window to come into contact with the copper metallized layer. Thereafter, the aluminum layer 74 is masked with a mask 76, the aluminum layer 74 and the barrier layer 73 are etched to form an aluminum bonding pad 77, the mask 76 is removed off, and a gold wire is bonded by thermocompression. By this setup, a gold wire can be bonded to a copper metallized layer.

公开(公告)号：JP2001244268A

公开(公告)日：2001-09-07

申请号：JP2001011600

申请日：2001-01-19

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method wherein a chip connection (controlled collapse chip connection: C4) which performs connection to the outside by Cu wiring and which controls corrosion and a wire bonding can be used in an integrated circuit. SOLUTION: (A) A conductor segment on the integrated circuit which comprises a contact region for electric connection is provided. (B) A bonding pad is provided. (C) A conductive barrier layer which is arranged between the contact region and the bonding pad is provided. The movement of the component of the conductor segment to the bonding pad from the contact region is prevented.

公开(公告)号：JP2000315689A

公开(公告)日：2000-11-14

申请号：JP2000120437

申请日：2000-04-21

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  KELLY MICHAEL JAMES

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To form an economical compact semiconductor circuit, etc., by forming an LDD area, a drain area, etc., by ion implantation after an ion implantation barrier is formed on a polysilicon material and treating the upper surface of the insulating barrier so that the upper surface may be flushed with the upper surface of an insulating layer. SOLUTION: A multilayered dual polysilicon structure 50 is provided with a first insulating layer 12 which has an upper surface 18, is formed on a substrate 10, and is preferably composed of silicon dioxide. In an appropriate embodiment, the upper surface 34 of the substrate 10 is exposed by etching first trenches 14 to thicknesses which are nearly equal to the thickness of the first insulating layer 12. It is ideal to form a second trench 16 after the first trenches 14 are formed in such a way that the trench 16 is shallower than the trenches 14 and has the upper surface 32 of the insulating layer 12 above the upper surface 34 of the substrate 10. The depth of the trench 16 varies depending upon the desired characteristics of an integrated circuit or device which is in the course of manufacture.

公开(公告)号：JPH10209297A

公开(公告)日：1998-08-07

申请号：JP36017697

申请日：1997-12-26

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  COCHRAN WILLIAM THOMAS ,  KNIGHT STEPHEN

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To form a pair of walls free from step-difference. SOLUTION: A first material layer 17 is deposited on the surface of a substrate 13. First type dopant species are injected 191 through the surface of the substrate 13. A second material layer is deposited on a pad oxide layer 15, and the first material layer 17 is eliminated. Second type dopant species are injected 192 through the eliminated region.

公开(公告)号：JP2001298029A

公开(公告)日：2001-10-26

申请号：JP2000381501

申请日：2000-12-15

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  COCHRAN WILLIAM THOMAS ,  IHYUUDA SUMUUHA

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a bonded pad structure that can utilize a region below a bonded pad for an active device. SOLUTION: A method for forming a dual etching bonded pad inside an integrated circuit has a resistance property to stress effect, and can form the bonded pad on an active circuit. The opening part of the bonded pad having a barrier film on a bottom surface at the upper part of the opening part is formed, thus forming the dual etching structure, and a via that passes through the bottom surface to extend downward. The barrier film forms the bottom surface at the upper part of the opening part of the bonded pad, and includes the via that passes through the bottom surface for extending to form the dual etching structure. The bonded pad is strong against stress effect such as cracking that may occur when external wiring is bonded to the bonded pad.

公开(公告)号：JPH09186168A

公开(公告)日：1997-07-15

申请号：JP32632296

申请日：1996-12-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  KNIGHT STEPHEN

IPC: H01L21/324

Abstract: PROBLEM TO BE SOLVED: To uniformly and more satisfactorily heat treat a wafer having a partly formed integrated circuit by coating the lover side of the wafer with a heat absorptive material and heating it with leaving specified distance from a heating surface. SOLUTION: The lower side of a wafer having a partly formed integrated circuit at the upper side 13 with a heat absorptive material and heated with leaving specified distance d from a heating surface 19. The bottom surface (lower side) of a Si wafer 11 is, e.g. coated with a heat absorptive material 15 such as C and held with a holding material 17 with leaving specified distance d from a heating surface 19 while the surface (upper side) 13 is directed up. The heating surface 19 is heated by the resistive heating of a hot plate or the like or by a lamp or hot gas to hold it at a fixed high temp.

公开(公告)号：GB2364170A

公开(公告)日：2002-01-16

申请号：GB0030319

申请日：2000-12-12

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  COCHRAN WILLIAM THOMAS ,  SMOOHA YEHUDA

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A dual damascene bond pad (27) resistant to stress effects within an integrated circuit is disclosed, allowing for the bond pad (27) to be formed over a substrate (1) containing active circuitry. The dual damascene structure is created by forming bond pad opening (20) and vias (19) in region (40), and depositing metal film (17) in the opening (20) and vias (19). The opening has barrier layer film (13) on bottom surface of opening (20) and vias (19) extending downwardly through barrier layer film (13) and lower dielectric film (11). A conductive layer (5) may be interposed between substrate region (1) and lower dielectric film (11). The reduction in stress of bond pad (27) results in the pad (27) being more resistant to cracking when an external wire (25) is attached to the pad (27), thus preventing leakage currents between the bond pad (27) and any underlying circuitry.

公开(公告)号：GB2356973A

公开(公告)日：2001-06-06

申请号：GB0019487

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHITTIPEDDI SAILESH ,  MERCHANT SAILESH MANSINH

IPC: H01L23/522 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A process for manufacturing a dual damascene structure for an integrated circuit involves forming a first opening (125) in a stack of layers including a first layer (105), second layer (115) and an etch stop layer (110), and forming a second opening (135) larger than the first opening (125). The first opening (125) is formed in a portion of the base of the first opening (125). Preferably the first opening (125) is formed before the second opening (135). The etch stop layer (110) may be a hardmask, and the first (105) and second (115) layers may be dielectrics. The two openings may be filled with conductive material (145) to create vias and interconnects for an integrated circuit. Patterned masks (120, 130) may be used to produce the dual damascene structure, where the mask used to create the second opening (130) is deposited over the mask used to create the first opening (120).