公开(公告)号：JP2000031811A

公开(公告)日：2000-01-28

申请号：JP14089099

申请日：1999-05-21

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K19/0175 ,  H03K19/003 ,  H03K19/0185

Abstract: PROBLEM TO BE SOLVED: To provide output buffer performance regardless of external factors and linear over the operating voltage range of an output driver by the device of resistors and transistors. SOLUTION: An output buffer for integrated circuit equipped with a predrive step 12 and an output driver step 14 is provided. The output driver step 14 is provided with a pull-up resistor device having parallelly connected plural branch parts and at least one pull-down resistor device in the similar configuration. A pull-up transistor is replaced with a pull-up control transistor and a pull-up data transistor. Similarly, the pull-down transistor is replaced with a pull-down control transistor and a pull-down data transistor. According to control information received from a control bit terminal 24, the resistance of the output buffer is regulated so as to correct the fluctuation of surrounding temperature, operating voltage and process.

公开(公告)号：JPH11168359A

公开(公告)日：1999-06-22

申请号：JP22262798

申请日：1998-08-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K3/356 ,  H03M9/00

Abstract: PROBLEM TO BE SOLVED: To drastically reduce the setup/holding time by generating an output signal having a first or second signal scale based on the scale of an input signal at the terminal of an initialization mode at an output mode. SOLUTION: Input switches 140 and 145 are opened as a result that a clock signal CLK is changed to a first signal level. The voltage scales of the parts IN and the inverse of IN of respective input signals at transistors 112 and 132 are kept in scales when the switches are opened irrespective of the subsequent change of the input signal parts during the period of the output mode. Namely, second and fourth transistors 110 and 130 are kept in a biased state to the same level as that given by the input signal parts IN and the inverse of IN at a moment when the clock signal CLK is shifted to a first signal period from a second signal period. An initialization switch 150 is opened with the shift and first and second junction parts 115 and 135 are mutually cut and they operate with the different voltage scale.

公开(公告)号：JPH10190709A

公开(公告)日：1998-07-21

申请号：JP27597997

申请日：1997-10-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  MORRIS BERNARD LEE

IPC: H04B3/02 ,  H04B3/40 ,  H04L12/42

Abstract: PROBLEM TO BE SOLVED: To reduce signal transmission delay between devices without hardly increasing power dissipation. SOLUTION: Impedance elements which can be switched in devices 101-106 connected to a closed loop signal bus 110 are used. The impedance elements selectively operate so that valid terminal impedance is generated in the position of an almost middle point from the connection point of the transmission device along the closed loop bus 110. A signal transmitted by the transmission device is transmitted as a clockwise signal and an anticlockwise signal along the closed loop bus 110. A device connection position to the closed loop bus 110 and the impedance value of the impedance elements which can be switched are selected so that they can selectively operate individually or by combining them in such a way that the elements generate the valid terminal impedance of the position of the almost middle point along the closed loop bus 110.

公开(公告)号：JPH10145217A

公开(公告)日：1998-05-29

申请号：JP15402197

申请日：1997-06-11

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K19/0175 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To reduce the necessity for the resistance of a discrete element by disposing a controllable impedance arrangement within the input/output port of an integrated circuit by on chip. SOLUTION: A controllable impedance arrangement 110 which is to be connected to an interface connected to an input/output buffer 105, and a communication line 115 is included in adaptive input/output ports 100 and 150. In this case, an interface 103 generally directs a conductive element, enabling the connection between the impedance arrangement 110 and the communication line 115. This controllable impedance arrangement 110 has three switchable impedance elements 120, 125 and 130 connected to respective corresponding sources VR, VP and VSS. Then, this controllable impedance arrangement 110 realizes the specified mutually different impedance to signals transmitted in their corresponding signal levels, and when receiving a data signal, it realizes a terminal impedance.

公开(公告)号：JPH1022811A

公开(公告)日：1998-01-23

申请号：JP6054297

申请日：1997-03-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K19/0175 ,  H03K19/017

Abstract: PROBLEM TO BE SOLVED: To obtain the enhanced integrated circuit, without the need for a large sized capacitor and/or complicated coding by generating a quantization feedback generated at a transient attenuation rate to compensate for the attenuation of a digital input signal through capacitance-coupling. SOLUTION: The integrated circuit 1 adopts a quantization feedback reception circuit that generates a complementary feedback signal SF and combines it with a capacitance-coupling input signal SO. The resulting combined signal SC is a signal, substantially compensating the attenuation of a received signal S1 for its attenuation period, so that the signal SC is restored to a voltage level detected by the integrated circuit 1, even for the period described above. Digital information in the resulting combined signal SC is detected by other part of the integrated circuit 1 or other integrated circuit 1, without substantial errors. Thus, coding/decoding of the communication signal is not required, and a complicated circuitry is avoided and power consumption is reduced.

公开(公告)号：DE69737731T2

公开(公告)日：2008-02-07

申请号：DE69737731

申请日：1997-06-17

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K19/0175 ,  H04L25/02 ,  H03K19/00

Abstract: A controllable impedance arrangement (110) is used in an adaptable input-output port (100,150) of an integrated circuit configuration (101,151) to enable the port to advantageously adapt its impedance according to whether its transmitting or receiving a communication signal. The controllable impedance arrangement (110) provides different specific impedances (120,125,130) for transmitting signals at respective signal levels, or a terminating impedance when receiving a data signal. This impedance arrangement (110) enables the input-output port and corresponding integrated circuit to have compact dimensions relative to conventional integrated circuits.

公开(公告)号：DE69733392D1

公开(公告)日：2005-07-07

申请号：DE69733392

申请日：1997-09-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  MORRIS BERNARD LEE

IPC: H04B3/02 ,  H04B3/40 ,  H04L12/42 ,  H04L25/02

Abstract: A communication system (100) having communicating devices (101-106) coupled to a closed loop bus (110) substantially reduces interconnect distances and corresponding signal propagation delays between the devices. Particular devices possess switchable impedance elements that can be selectively actuated to produce an effective terminating impedance substantially at a midpoint position along the closed loop from the coupling point of a transmission device. In such an arrangement, the produced effective terminating impedance would cause the signal transmitted by the transmission device to propagate to a destination device substantially without signal degradation due to signal reflections.

公开(公告)号：DE60139440D1

公开(公告)日：2009-09-17

申请号：DE60139440

申请日：2001-05-14

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MUJTABA SYED AON ,  GABARA THADDEUS JOHN

IPC: H01Q3/26 ,  H04W16/32 ,  H04B7/26 ,  H04W88/08

公开(公告)号：DE69828226T2

公开(公告)日：2005-12-15

申请号：DE69828226

申请日：1998-07-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: H03K3/356 ,  H03M9/00

Abstract: A novel latch circuit configuration (100) that substantially reduces inverter-based setup and hold times includes first and second input switches (140, 145) connected to an effective sense amplifier configuration. It is possible for the input switches to receive complimentary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.

公开(公告)号：CA2314400C

公开(公告)日：2004-05-25

申请号：CA2314400

申请日：2000-07-21

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MUJTABA SYED AON ,  GABARA THADDEUS JOHN

IPC: H03M5/12 ,  H03M5/16 ,  H04B14/00 ,  H04J1/00 ,  H04J11/00 ,  H04L5/02 ,  H04L25/49

Abstract: Two or more digital signals are encoded using two or more respective li ne codes. The line codes are chosen in conjunction with the data rates of the digital signals such that the encoded signals are substantially orthogonal to each other in the frequency domain. As such, the two or more encoded signals may be combin ed and transmitted via a single physical medium with little or no interference. A transmitter for encoding and transmitting the digital signals contains line coders for encoding the digital signals and a combiner for combining the encoded signal s for transmission via a single physical medium. A receiver for receiving and decoding the combined encoded signal contains filters for extracting the individual encoded signals and line decoders for decoding the individual encoded signals to generate the original digital data signals.