公开(公告)号：JP2002026806A

公开(公告)日：2002-01-25

申请号：JP2001141358

申请日：2001-05-11

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  MUJITABA SYED AON

IPC: H01Q3/26 ,  H04B7/26 ,  H04W16/32 ,  H04W88/08

Abstract: PROBLEM TO BE SOLVED: To provide a system including a new micro cell for solving the problem of a communication system including a conventional micro cell. SOLUTION: In one performing example of the system, the base station of the micro cell has a two-dimensional(2D) antenna array coexisting with the antenna of the macro cell. This two-dimensional antenna array is constituted so that its direction can be converted in both of a horizontal direction and a vertical direction. The extent of the coverage area of the micro cell depends on a distance from the antenna of a cell site and the dimension of the array for deciding the angle diffusion of beams.

公开(公告)号：JPH10313244A

公开(公告)日：1998-11-24

申请号：JP8196698

申请日：1998-03-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  RUDNICK ROBERT E

IPC: G06F3/00 ,  H03K19/0175 ,  H04L12/40 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To reduce the distortion and ringing of a communication signal transmitted onto a bus transmission line while reducing driver power by connecting damping impedance to a component. SOLUTION: The integrated circuit component 20c has a controllable damping impedance element 60 inside. The impedance element 60 has an impedance element 66 and a switch 68 which are connected to an interface 46. In operation, the impedance element 66 is switched by a switch 68 between a closure position connected to the component 20c and an opening position which is separated. The characteristic value of the impedance element 66 is selected according to, for example, a signal level which should be sent onto the bus transmission line 24.

公开(公告)号：JPH11168370A

公开(公告)日：1999-06-22

申请号：JP27394598

申请日：1998-09-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  BIJATTO SAKOOBAHI PATEL ,  WAINE E WARNER

IPC: G06F3/00 ,  H03F3/345 ,  H03K17/041 ,  H03K17/16 ,  H03K17/687

Abstract: PROBLEM TO BE SOLVED: To provide a current output circuit for not generating switching noises due to the ON/OFF of the current of respective current drivers when a data state is changed. SOLUTION: The current output circuit 10 is provided with the current drivers 20 and 26 connected to a first and second output nodes 32 and 34 by current switches 36, 40, 44 and 46 for supplying the current I and a switchable shunt resistor 48 connected to the current drivers. The current supplied by the driver is shunted through the switchable shunt resistor 48 and the current from the driver is kept fixed and does not contribute to a net load current. For the current switch, in a first data state, the current supplied by the current driver is made to flow from the first output node 32 to the second output node 34 and the current I is supplied to a connected load 50. In a second data state, the current is made to flow from the second output node 34 to the first output node 32 and the current -I is supplied to the load 50.

公开(公告)号：JPH10289976A

公开(公告)日：1998-10-27

申请号：JP11419098

申请日：1998-04-09

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  TAI KING L

IPC: H01L23/50 ,  H01L23/538 ,  H01L25/065

Abstract: PROBLEM TO BE SOLVED: To enable ICs to be integrated into a multi-chip module by a method wherein a first chip is equipped with a first and a second circuit part which are connected together with a signal conductor, the first and second chip are connected direct together with the signal conductor of the first chip, and the second circuit part of the first chip is bypassed. SOLUTION: ICs 111 and 121 are equipped with signal processing circuits 112 and 122 (first circuit part) respectively, and furthermore the ICs 111 and 121 are provided with conductor IC buses 113 and 123 respectively so as to store data in common. Moreover, the ICs 111 and 121 are provided with a serial input/output port (second circuit part) connected to the IC buses 113 and 123 respectively. At this point, a multi-chip module 200 is furthermore equipped with a lead 230 (mutual connecting means) which connects the IC bus 113 of the IC 111 to the IC bus 123 of the IC 121. By this setup, the buffers of a multiplex circuit and the ICs 111 and 121 can be bypassed.

公开(公告)号：JP2001111536A

公开(公告)日：2001-04-20

申请号：JP2000243514

申请日：2000-08-11

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  ADRIAN PATRICK RAINAMU

IPC: G06F13/42 ,  G06F1/12 ,  H03L7/081 ,  H03L7/091 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04

Abstract: PROBLEM TO BE SOLVED: To provide technology regarding synchronization technology suitable to be used in the case of unknown correspondence relation, such as unknown or uncertain phase relation or for use with data transfer between circuits to be operated by an uncertain signal, and other signal processing technology regarding electronic circuits. SOLUTION: The circuit of a device includes first, second and third processing circuit 14-1, 14-2, 14-3, each of which executes a sampling function by using clock signals with which prescribed signal is to be synchronized regarding one corresponding version of an initial, a middle and a last versions of the prescribed signal. A logic circuit 16 to be connected with each output of the first, second and third processing circuit generates a control signal to indicate presence/absence of necessary phase relation among the clock signal and the first, second and third versions of the specified signal. Then when absence of the necessary correspondence relation is indicated by the control signal, a selecting circuit changes the phase relation among the clock signal and the first, second and third versions of the specified signal according to the control signal.

公开(公告)号：JP2000236266A

公开(公告)日：2000-08-29

申请号：JP2000020262

申请日：2000-01-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  MOERZ MATTHIAS

IPC: G06G7/24 ,  H03M13/41

Abstract: PROBLEM TO BE SOLVED: To obtain an analog encoder decoder by providing a 1st-layer block and an index load device connected between one of type-B output terminals of a layer block and a fixed-potential point. SOLUTION: This device is equipped with a 1st-layer block and index load device. The 1st layer block has two active device, having terminals of three types, a terminal of one type of the active devices is connected to a common point connected to the type-A output lead of the 1st-layer block, and terminals of other types are coupled to the output leads of types B of the layer blocks. The index load device is connected between one of type-B output terminals of layer blocks and the fixed potential point. For example, npn transistors 41 to 43 are shown for a layer block 100, the emitters of the transistors 41 to 43 are all interconnected to form the type-A output lead of the layer block 100, and the collectors are connected to the type-B output lead of the layer block 100.

公开(公告)号：JPH1185343A

公开(公告)日：1999-03-30

申请号：JP17429198

申请日：1998-06-22

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN

IPC: G06F3/00 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

Abstract: PROBLEM TO BE SOLVED: To provide LVDS I/O buffers maintaining high speed data transfer between package devices on a printed circuit board and between different back planes. SOLUTION: The operation points of LVDS input/output buffers 11 and 12 are biased by voltage generated by a reference feed back circuit. Output buffer voltage, current and input buffer impedance are kept constant regardless of all processes, voltage and temperature conditions. Thus, the voltage logic level of transfer data also becomes constant. The reference circuit 45 can generate bias voltage for all input/output buffers on a chip by using one inner or outer reference resistor REXT, reference voltage VHIGH and VLOW.

公开(公告)号：JP2002208639A

公开(公告)日：2002-07-26

申请号：JP2001331207

申请日：2001-10-29

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  TAREKU CHAKER JOMAR

IPC: G03F1/08 ,  G06F17/50 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528

Abstract: PROBLEM TO BE SOLVED: To provide an IC manufacturing technique for wiring a wire aslant on an IC chip, and to provide a method of reducing a mutual connecting distance, while preventing waved wires. SOLUTION: As a first step, a non-horizontal/non-vertical connecting line of an integrated circuit is assigned to a different metal mask layer from the metal mask, layer that is assigned to at least one of a horizontal mutual connecting line and a vertical mutually connecting line. Next, the non-horizontal/ non-vertical mutually connecting line is turned by predetermined degree from the original direction. Finally, the non-horizontal/non-vertical mutually connecting line is directed to at least one direction out of the horizontal and vertical directions, and the turned non-horizontal/non-vertical mutually connecting line is printed on the metal mask layer, to which it is assigned.

公开(公告)号：JP2001203315A

公开(公告)日：2001-07-27

申请号：JP2000362327

申请日：2000-11-29

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  JERICHIO J JAKARA ,  O'CONNOR KEVIN JOHN ,  TAI KING L

IPC: H01L21/66 ,  H01L25/04 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To provide a single integrated cluster chip having a plurality of chip sites packaged in an IC package of a maltichip module-(MCM). SOLUTION: A fully functioning cluster of chip sites or an almost fully functioning chip sites is identified by a wafer level test. The cluster is individualized as a single chip, and packaged. One cluster may contain, for example, a combination of chip types such as a combination of memories and logic circuits. The cluster normally includes 3 to 25 pieces of chip sites. Two or more types of clusters can be identified and created on a single wafer. The remaining fully functioning chips are individualized as individual chips, and can be packaged as a single chip package or in any of the MCM by a conventional method. Mutually connected substrates are added with an arrangement configuration of silicon-on-silicon to the cluster, and a plurality of chip sites can be connected to each other.

公开(公告)号：JP2001069120A

公开(公告)日：2001-03-16

申请号：JP2000226696

申请日：2000-07-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GABARA THADDEUS JOHN ,  MUJTABA SYED AON

IPC: H03M5/12 ,  H03M5/16 ,  H04B14/00 ,  H04J1/00 ,  H04J11/00 ,  H04L5/02 ,  H04L25/49

Abstract: PROBLEM TO BE SOLVED: To provide signal encoding for transmitting plural digital signals through a single physical medium. SOLUTION: Digital signals more than two are encoded using respective line codes more than two. The line code is selected from combination with the data rate of the digital signal so that encoded signals can be mutually practically orthogonal in a frequency domain. Then, encoded signals more than two can be combined and transmitted almost or completely without interference. A transmitter 602 for encoding and transmitting digital signals is provided with a coder for encoding digital signals and a combiner for combining the signals encoded for transmission through a single physical medium. A receiver 620 for receiving and decoding the combined and encoded signals is provided with a filter for extracting each of encoded signals and a line decoder for decoding each of encoded signals for generating original digital data signals.