公开(公告)号：WO1994029841A1

公开(公告)日：1994-12-22

申请号：PCT/US1994006758

申请日：1994-06-14

Applicant: MICRON DISPLAY TECHNOLOGY, INC.

Inventor： MICRON DISPLAY TECHNOLOGY, INC. ,  BROWNING, Jim, J. ,  HUSH, Glen, E. ,  LEE, John, K.

IPC: G09G03/10

CPC classification number: G09G3/22 ,  G09G3/2011 ,  G09G2300/08 ,  G09G2310/0248 ,  H01J31/127 ,  H01J2201/319

Abstract: A field emission display (110) of the active matrix type is arranged in rows and columns with a current source (126) for each column. As an active matrix display, each pixel circuit (118) in an array of pixel circuits (116) includes a switch for enabling display by that pixel circuit. By locating the current source (126) outside the array (116), for example outside a contour circumscribing the array when the display is formed on a susbstrate, smaller pixel circuit geometries are achieved.

Abstract translation: 有源矩阵类型的场发射显示器（110）以行和列布置，每列具有电流源（126）。 作为有源矩阵显示器，像素电路（116）阵列中的每个像素电路（118）包括用于使该像素电路能够显示的开关。 通过将电流源（126）定位在阵列（116）外部，例如当在显示器形成在突起上时围绕阵列的轮廓外部，实现较小的像素电路几何形状。

公开(公告)号：WO1998014931A1

公开(公告)日：1998-04-09

申请号：PCT/US1997017884

申请日：1997-10-03

Applicant: MICRON DISPLAY TECHNOLOGY, INC.

Inventor： MICRON DISPLAY TECHNOLOGY, INC. ,  HUSH, Glen, E.

IPC: G09G03/20

CPC classification number: G09G3/20 ,  G09G2310/0275 ,  G09G2310/08 ,  H03L7/0812 ,  H04N5/66

Abstract: A matrix addressable display includes a delay locked loop formed from a delay chain formed from several variable delay blocks and a comparator. The delay locked loop receives a horizontal sync portion of an image signal and propagates the horizontal sync through the chain of delay blocks. The output of the last delay block drives the comparator that also receives an undelayed horizontal sync component. The comparator compares the undelayed horizontal sync to the delayed horizontal sync component and produces an error signal corresponding to the phase difference. The error signal is input to each of the delay blocks. In response to the error signal, the delay of the respective delay blocks increases or decreases to reduce the phase difference between the undelayed horizontal sync component and the delayed sync component. In addition to driving the delay chain, the horizontal sync component also walks a "1" through a row driver to sequentially activate rows of the array.

Abstract translation: 矩阵可寻址显示器包括由由多个可变延迟块和比较器形成的延迟链形成的延迟锁定环。 延迟锁定环接收图像信号的水平同步部分并且通过延迟块链传播水平同步。 最后一个延迟块的输出驱动也接收未延迟的水平同步分量的比较器。 比较器将未延迟的水平同步与延迟的水平同步分量进行比较，并产生与相位差对应的误差信号。 误差信号被输入到每个延迟块。 响应于误差信号，各个延迟块的延迟增加或减小，以减少未延迟的水平同步分量和延迟的同步分量之间的相位差。 除了驱动延迟链之外，水平同步分量还通过行驱动器进行“1”，以依次激活阵列的行。

公开(公告)号：WO1997004482A1

公开(公告)日：1997-02-06

申请号：PCT/US1996011643

申请日：1996-07-12

Applicant: MICRON DISPLAY TECHNOLOGY, INC. ,  LEE, John, K. ,  CATHEY, David, A., Jr. ,  TJADEN, Kevin

Inventor： MICRON DISPLAY TECHNOLOGY, INC.

IPC: H01L21/70

CPC classification number: H01L28/24 ,  H01J9/025 ,  H01J2201/319 ,  H01L28/20

Abstract: A method for forming resistors for regulating current in a field emission display (10) comprises integrating a high resistance resistor (32) into circuitry for the field emission display. The resistor (32) is in electrical communication with emitter sites (14) for the field emission display (10) and with other circuit components such as ground. The high resistance resistor (32) can be formed as a layer of a high resistivity material, such as intrinsic polycrystalline silicon, polycrystalline silicon doped with a conductivity-degrading dopant, lightly doped polysilicon, titanium oxynitride, tantalum oxynitride or a glass type material deposited on a baseplate (12) of the field emission display (10). Contacts (38, 39) are formed in the high resistivity material to establish electrical communication between the resistor (32) and the emitter sites (14) and between the resistor (32) and the other circuit components. The contacts (38, 39) can be formed as low resistance contacts (e.g., ohmic contacts) or as high resistance contacts (e.g., Schottky contacts).

Abstract translation: 一种用于形成用于调节场发射显示器（10）中的电流的电阻的方法包括将高电阻电阻（32）集成到用于场发射显示的电路中。 电阻器（32）与用于场发射显示器（10）的发射器位置（14）和与其它电路部件（例如接地）电连通。 高电阻电阻（32）可以形成为诸如本征多晶硅，掺杂有导电性降解掺杂剂的多晶硅，轻掺杂多晶硅，氮氧化钛，氮氧化钽或沉积的玻璃类材料的高电阻率材料的层 在场发射显示器（10）的基板（12）上。 在高电阻率材料中形成触点（38,39），以在电阻器（32）和发射极部分（14）之间以及电阻器（32）和其它电路部件之间建立电连通。 触点（38,39）可以形成为低电阻触点（例如欧姆接触）或高电阻触点（例如，肖特基触点）。

公开(公告)号：WO1996024944A1

公开(公告)日：1996-08-15

申请号：PCT/US1996001657

申请日：1996-02-08

Applicant: MICRON DISPLAY TECHNOLOGY, INC.

Inventor： MICRON DISPLAY TECHNOLOGY, INC. ,  CATHEY, David, A. ,  GOCHNOUR, Derek ,  WATKINS, Charles

IPC: H01J09/26

CPC classification number: H01L25/50 ,  H01J9/241 ,  H01J9/261 ,  H01J9/32 ,  H01J9/36 ,  H01J2329/8625 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H05K3/328 ,  H05K3/368 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: The disclosure describes a method of attaching and electrically connecting first and second planar substrates, wherein the first and second substrates have inwardly-facing surfaces with matching patterns of bond pads (72). The method includes adjusting a wire bonder's tear length to a setting which leaves a projecting tail (80) of severed bond wire at a terminating wedge bond connection. Further steps include making a wedge bond to an individual bond pad of the first planar substrate with bond wire from the wire bonder, and then severing the bond wire adjacent said wedge bond. The adjusted tear length of the wire bonder results in a tail of severed bond wire which projects from said wedge bond and said individual bond pad. Subsequent steps include positioning the first and second planar substrates with their inwardly-facing surfaces facing each other, aligning the matching bond pad patterns of the first and second planar substrates, and pressing the first and second planar substrates against each other. The bond wire tail (80) deforms between the bond pads of the first and second planar substrates to conductively bond therebetween.

Abstract translation: 本公开描述了一种附接和电连接第一和第二平面基板的方法，其中第一和第二基板具有具有匹配图案的接合焊盘（72）的向内表面。 该方法包括将引线接合器的撕裂长度调整到在终止楔形结合连接处留下断开的接合线的突出尾部（80）的设置。 进一步的步骤包括使用与引线接合器的接合线将第一平面基片的单个接合焊盘楔合，然后切断邻近所述楔形键的接合线。 引线接合器的经调整的撕裂长度导致从所述楔形键和所述单独接合焊盘突出的断开的接合线的尾部。 随后的步骤包括将第一和第二平面基板定位成其面向彼此的向内表面，使第一和第二平面基板的匹配接合焊盘图案对准，并将第一和第二平面基板相互按压。 接合线尾（80）在第一和第二平面基板的接合焊盘之间变形，以在它们之间导电地结合。