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公开(公告)号：US11532373B2
公开(公告)日：2022-12-20
申请号：US17205091
申请日：2021-03-18
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.
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公开(公告)号：US11360677B2
公开(公告)日：2022-06-14
申请号：US16948305
申请日：2020-09-11
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Karl D. Schuh , Jiangang Wu , Mustafa N. Kaynak , Devin M. Batutis , Xiangang Luo
IPC: G06F3/06
Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.
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公开(公告)号：US11017870B1
公开(公告)日：2021-05-25
申请号：US16798832
申请日：2020-02-24
Applicant: Micron Technology, Inc.
Inventor： Devin M. Batutis , Avinash Rajagiri , Sheng-Huang Lee , Chun Sum Yeung , Harish R. Singidi
Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.
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公开(公告)号：US20240231676A1
公开(公告)日：2024-07-11
申请号：US18616006
申请日：2024-03-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Devin M. Batutis , Xiangang Luo , Mustafa N. Kaynak , Peter Feeley , Sivagnanam Parthasarathy , Sampath Ratnam , Shane Nowell
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0655 , G06F3/0679
Abstract: An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
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公开(公告)号：US11966616B2
公开(公告)日：2024-04-23
申请号：US18175439
申请日：2023-02-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Devin M. Batutis , Xiangang Luo , Mustafa N. Kaynak , Peter Feeley , Sivagnanam Parthasarathy , Sampath Ratnam , Shane Nowell
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0655 , G06F3/0679
Abstract: A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
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Patent Agency Ranking
公开(公告)号：US11709727B2
公开(公告)日：2023-07-25
申请号：US17216901
申请日：2021-03-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Shane Nowell , Mustafa N. Kaynak , Sampath K. Ratnam , Peter Feeley , Sivagnanam Parthasarathy , Devin M. Batutis , Xiangang Luo
CPC classification number: G06F11/0793 , G06F11/0727 , G06F11/0751
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.
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公开(公告)号：US11620074B2
公开(公告)日：2023-04-04
申请号：US17203474
申请日：2021-03-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Devin M. Batutis , Xiangang Luo , Mustafa N. Kaynak , Peter Feeley , Sivagnanam Parthasarathy , Sampath Ratnam , Shane Nowell
Abstract: A current memory access voltage distribution is measured for a memory page of a block family associated with a first voltage bin of a plurality of voltage bins at a memory device. The first voltage bin is associated with a first voltage offset. A current value for a reference voltage is determined based on the current memory access voltage distribution measured for the memory page. An amount of voltage shift for the memory page is determined based on the current value for the reference voltage a prior value for the reference voltage. The prior value for the reference voltage is associated with a prior memory access voltage distribution for the memory page. In response to a determination that the amount of voltage shift satisfies a voltage shift criterion, the block family is associated with a second voltage bin of the plurality of voltage bins. The second voltage bin is associated with a second voltage offset.
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公开(公告)号：US11609846B2
公开(公告)日：2023-03-21
申请号：US16948302
申请日：2020-09-11
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Karl D. Schuh , Jiangang Wu , Mustafa N. Kaynak , Devin M. Batutis , Xiangang Luo
IPC: G11C11/00 , G06F12/02 , G06F12/0846 , G06F12/0882 , G11C16/26 , G11C16/34 , G11C16/10
Abstract: A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device is to perform operations, including receiving a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The operations further include partitioning the set of pages into a set of partitions, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the set of pages is partitioned.
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公开(公告)号：US11587639B2
公开(公告)日：2023-02-21
申请号：US17198755
申请日：2021-03-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Xiangang Luo , Peter Feeley , Devin M. Batutis , Jiangang Wu , Sampath K Ratnam , Shane Nowell , Karl D. Schuh
Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.
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公开(公告)号：US11501840B1
公开(公告)日：2022-11-15
申请号：US17243386
申请日：2021-04-28
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Devin M. Batutis
Abstract: A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.
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