Abstract:
The present invention discloses a device and method for use in a clocking requirement, wherein the device in accordance with the preferred embodiments of the present invention aids to synchronize in the event that there are two different clock sources. The device comprises; a means for receiving frequency input clock and derive output clock frequency; a means to convert serial to parallel data and configure first frequency doubler and output selector; a means for generating a primary clock as a reference signal; a means for receiving input signals frequency doublers and driving larger output load; and a means for selecting a plurality of doubled signals from a clock driver output.
Abstract:
A read-out interface circuitry (ROIC) (10) connectable to a sensor (29) is provided, the ROIC (10) includes at least one phase detector circuit (20) to compare phase difference between an input reference signal and an output signal from the sensor (29), and at least one charge pump circuit (40) connectable to the at least one phase detector circuit (20) wherein an output of the at least one charge pump circuit (40) is convertible to a direct current (DC) voltage.
Abstract:
For a SAR ADC with having an integrated programmable voltage reference function, a process for the voltage programmable positive voltage reference integrated to SAR ADC, includes; a) integrating a bandgap (21) to provides a stable voltage b) scaling up to a higher voltage by first Opamp (22) from the bandgap (21) and the voltage divided by the first resistor string (24) and second resistor string (25) to provides taps for the different voltage levels c) buffering the voltage at second Opamp (23) d) transferring the voltage to the decoding network (28) e) decoding the voltage by the decoder having at least one signal (29) and connecting the voltage to at least one resistor string (27) and at least one resistor string (27) tap point to the input third Opamp (30) f) buffering the voltage at the third Opamp (30) and the output becoming voltage reference programmable g) used as voltage reference at the digital-to-analog DAC (12) and the output of the converted voltage becoming voltage digital-to-analog (Vdac) h) sending the Vdac to the comparator (13) and the output of the comparator sending to the SAR (11) i) modifying the Vdac contents bit by bit until the data are the digital equivalent of the analog input j) repeating steps (a) through (i) until a predetermined number of trials have been completed.