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    READOUT INTERFACE CIRCUIT FOR FEF SENSOR
    1.
    发明专利
    READOUT INTERFACE CIRCUIT FOR FEF SENSOR 未知

    公开(公告)号：MY173896A

    公开(公告)日：2020-02-26

    申请号：MYPI20090198

    申请日：2009-01-16

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN ,  ROZAIMAH BAHARIM

    Abstract: A readout interface circuit for a humidity sensor, particularly FEF sensor (10) is described. The readout interface circuit comprises a phase detector (20), a charge pump (30), a half wave rectifier (50) and two low pass filters (40, 42). The phase detector (20) is configured to produce output voltage proportional to the phase difference of signals from FEF sensor. The charge pump (30) is configured to control the current flow of phase detector to provide a linear output of phase detector. The first low pass filter (40) suppress noise level of charge pump output. The half wave rectifier (50) extracts the signal magnitude of sensor output. The second low pass filter (42) extract DC level of output of half wave rectifier. The output of first low pass filter (40) carries phase difference information of humidity and the output of second low pass filter (42) carries voltage output of humidity.

    A PROGRAMMABLE TWO-PHASE NON-OVERLAPPING CLOCK SIGNAL SELF-GENERATOR
    2.
    发明专利
    A PROGRAMMABLE TWO-PHASE NON-OVERLAPPING CLOCK SIGNAL SELF-GENERATOR 未知

    公开(公告)号：MY162256A

    公开(公告)日：2017-05-31

    申请号：MYPI20093560

    申请日：2009-08-27

    Applicant: MIMOS BERHAD

    Inventor： WEE LEONG SON ,  YUZMAN YUSOFF

    IPC: G06F1/06 ,  G06F7/487 ,  H03K5/15

    Abstract: THE PRESENT INVENTION RELATES TO A CLOCK GENERATOR CIRCUIT (300) THAT IS PROGRAMMABLE AND CAPABLE OF SELF-GENERATING TWO-PHASE NON-OVERLAPPING CLOCK SIGNALS FOR SWITCH CAPACITOR CIRCUIT APPLICATIONS. THIS CLOCK GENERATOR CIRCUIT (300) HAS A WIDE FREQUENCY RANGE AND ALLOWS FOR SELECTION OF SEVERAL FREQUENCY RATES BY CONTROLLING THE DIGITAL INPUTS OF A MULTIPLEXER (330). BESIDES THE MULTIPLEXER (330), THE PROPOSED CIRCUIT INCLUDES A RING OSCILLATOR (310), FREQUENCY DIVIDERS (320) AND A TWO-PHASE NON-OVERLAPPING CLOCK CIRCUIT (340). THE INTERNAL RING OSCILLATOR (310) GENERATES AN OSCILLATION SIGNAL AND SENDS THE SIGNAL TO THE FREQUENCY DIVIDERS (320). THESE FREQUENCY DIVIDERS (320) GENERATE SERIES OF CLOCK SIGNALS AT DIFFERENT FREQUENCIES. THROUGH THE MULTIPLEXER (330), ONE OF THE CLOCK SIGNALS IS SELECTED AND TRANSFERRED TO THE NON-OVERLAPPING CLOCK CIRCUIT (340). THE NON-OVERLAPPING CLOCK SIGNAL GENERATOR (340) INCLUDES TOGGLE FLIP-FLOP, NAND GATES, DELAY AND BUFFER CELLS. THE MOST ILLUSTRATIVE DRAWING: FIG. 3

    A CONSTANT PULSE WIDTH GENERATOR
    4.
    发明专利
    A CONSTANT PULSE WIDTH GENERATOR 未知

    公开(公告)号：MY163408A

    公开(公告)日：2017-09-15

    申请号：MYPI2012701209

    申请日：2012-12-18

    Applicant: MIMOS BERHAD

    Inventor： HANIF CHE LAH ,  WEE LEONG SON ,  ROZITA BORHAN

    IPC: H03K3/017 ,  H03K5/156

    Abstract: THE PRESENT INVENTION GENERALLY PERTAINS TO A PULSE GENERATOR (100) AND A METHOD FOR PRODUCING PULSE, MORE PARTICULARLY THE PRESENT INVENTION PERTAINS TO A CONSTANT PULSE WIDTH GENERATOR AND A METHOD FOR PRODUCING CONSTANT PULSE WIDTH SIGNALS, WHEREIN THE PULSE GENERATOR (100) COMPRISES AN INPUT (11) FOR RECEIVING SIGNALS, A SIGNAL DETECTOR (12) FOR DETECTING SIGNAL LEVELS, A FREQUENCY DIVIDER (13) FOR DIVIDING FREQUENCY OF THE SIGNALS, AT LEAST A SIGNAL GENERATOR (14) FOR GENERATING PREDETERMINED PULSE WIDTH SIGNALS FROM THE FREQUENCY DIVIDED SIGNALS, AT LEAST AN INTEGRATOR (15) FOR INTEGRATING THE SIGNALS, AND AT LEAST AN OUTPUT (16) FOR PROVIDING CONSTANT PULSE WIDTH SIGNALS. MOST ILLUSTRATIVE DRAWING:

    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS
    5.
    发明专利
    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS 未知

    公开(公告)号：MY173978A

    公开(公告)日：2020-03-02

    申请号：MYPI20090068

    申请日：2009-01-08

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROZAIMAH BAHARIM ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN

    Abstract: An adaptable readout interface circuit ( 1 0) comprising three operational amplifiers (11, 12, 13), a plurality of resistors (25, 26, 27), an adjustable gain resistor (15) and an offset voltage provider ( 16) is described. The first operational amplifier ( 11) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. An ion sensor (17) coupled to the positive terminal of the first operational amplifier. The second operational amplifier (12) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. A reference electrode (18) coupled to the positive terminal of the second operational amplifier. A gain resistor (15) is coupled to the negative terminal of the third operational amplifier to configure the third operational amplifier (13) as a gain amplifier. The output voltage of third operational amplifier provides an adjusted sensitivity and direct current level of ion sensor reading

    METHOD AND SYSTEM FOR TRANSFERRING DATA THROUGH TWO DIFFERENT CLOCK DOMAINS
    6.
    发明专利
    METHOD AND SYSTEM FOR TRANSFERRING DATA THROUGH TWO DIFFERENT CLOCK DOMAINS 未知

    公开(公告)号：MY171066A

    公开(公告)日：2019-09-24

    申请号：MYPI2014003297

    申请日：2014-11-25

    Applicant: MIMOS BERHAD

    Inventor： ROZITA BORHAN ,  WEE LEONG SON ,  MUHAMAD KHAIROL BIN AB RANI

    Abstract: [0030] There is disclosed a system for transferring data between two asynchronous clock domains, thus having at least a source clock (first clock domain) and a receiving clock (second clock domain); the system comprising: a multiplexer (20) for providing the first input; a register (30, 90) configured for receiving and storing data input at the first clock domain (1) and second clock domain (2); a comparison module (40,70) at the first clock domain (1) and second clock domains (2) configured for receiving incoming data input comparing data inputs; a controller (50, 80) at the first clock domain (1) and second clock domain (2) configured to receive the comparison output and toggling at least one signal (in2out) if a data change is detected based on the comparison; at least one synchronizer (60) to synchronizes signals into the second clock domain (2).

    A WRAPPER CIRCUIT CAPABLE OF REDUCING LATENCY IN OPERATION BETWEEN INTERFACED MEMORY CONTROLLER AND MEMORY
    7.
    发明专利
    A WRAPPER CIRCUIT CAPABLE OF REDUCING LATENCY IN OPERATION BETWEEN INTERFACED MEMORY CONTROLLER AND MEMORY 未知

    公开(公告)号：MY174430A

    公开(公告)日：2020-04-17

    申请号：MYPI2011004287

    申请日：2011-09-12

    Applicant: MIMOS BERHAD

    Inventor： WEE LEONG SON ,  SUHAIMI BAHISHAM JUSOH @ YUSOFF

    Abstract: The present invention relates to a wrapper circuit (112) used for interfacing a non-muxed memory controller (101) and a muxed-memory. Particularly, the wrapper circuit (112) uses timing control select (TCS) input prompting one or more processing circuit to generate a data enable timing control signal ( 110) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory. The disclosed wrapper circuit ( 112) avoid any pre-fix clock cycles which probably contains more clock cycles than the minimum number needed to fulfill the minimum access time therefore the disclosed circuit promotes faster write operation between the interfaced non-muxed memory controller (101) and muxed memory. (Most illustrated by figure 1)

    READ-OUT INTERFACE CIRCUIT FOR MULTIPLE IONS SENSING
    9.
    发明申请
    READ-OUT INTERFACE CIRCUIT FOR MULTIPLE IONS SENSING 审中-公开
    用于多个离子感测的读出接口电路

    公开(公告)号：WO2009066984A3

    公开(公告)日：2009-10-15

    申请号：PCT/MY2008000149

    申请日：2008-11-21

    Applicant: MIMOS BERHAD ,  YUZMAN B YUSOFF ,  MOHAMAD FAIZAL B HASHIM ,  WEE LEONG SON

    Inventor： YUZMAN B YUSOFF ,  MOHAMAD FAIZAL B HASHIM ,  WEE LEONG SON

    IPC: H03K19/0175 ,  G06F13/00

    CPC classification number: G01N27/4148

    Abstract: A read out circuit for multiple ion sensing and method is disclosed. The said circuit (1) is composed of a plurality of sensors, preferably ISFET (5) sensors, a plurality of CIMP (2) circuits, an analog selector (4) and an analog to digital converter (6). Said circuit allows the sensors therein be operated simultaneously and thus processing time for output signal is reduced.

    Abstract translation: 公开了一种用于多离子感测和方法的读出电路。 所述电路（1）由多个传感器，优选ISFET（5）传感器，多个CIMP（2）电路，模拟选择器（4）和模数转换器（6）组成。 所述电路允许其中的传感器同时操作，因此减少输出信号的处理时间。

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