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    READOUT INTERFACE CIRCUIT FOR FEF SENSOR
    1.
    发明专利
    READOUT INTERFACE CIRCUIT FOR FEF SENSOR 未知

    公开(公告)号：MY173896A

    公开(公告)日：2020-02-26

    申请号：MYPI20090198

    申请日：2009-01-16

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN ,  ROZAIMAH BAHARIM

    Abstract: A readout interface circuit for a humidity sensor, particularly FEF sensor (10) is described. The readout interface circuit comprises a phase detector (20), a charge pump (30), a half wave rectifier (50) and two low pass filters (40, 42). The phase detector (20) is configured to produce output voltage proportional to the phase difference of signals from FEF sensor. The charge pump (30) is configured to control the current flow of phase detector to provide a linear output of phase detector. The first low pass filter (40) suppress noise level of charge pump output. The half wave rectifier (50) extracts the signal magnitude of sensor output. The second low pass filter (42) extract DC level of output of half wave rectifier. The output of first low pass filter (40) carries phase difference information of humidity and the output of second low pass filter (42) carries voltage output of humidity.

    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS
    3.
    发明专利
    ADAPTABLE READOUT INTERFACE CIRCUIT FOR ION SENSORS 未知

    公开(公告)号：MY173978A

    公开(公告)日：2020-03-02

    申请号：MYPI20090068

    申请日：2009-01-08

    Applicant: MIMOS BERHAD

    Inventor： NABIHAH RAZALI ,  ROZAIMAH BAHARIM ,  ROHANA MUSA ,  YUZMAN YUSOFF ,  MOHD SHAHIMAN SULAIMAN ,  HASMAYADI ABDUL MAJID ,  WEE LEONG SON ,  HANIF CHE LAH ,  ROHAYA ABDUL WAHAB ,  TAN KONG YEW ,  SHARIFAH SALEH ,  NAZALIZA OTHMAN

    Abstract: An adaptable readout interface circuit ( 1 0) comprising three operational amplifiers (11, 12, 13), a plurality of resistors (25, 26, 27), an adjustable gain resistor (15) and an offset voltage provider ( 16) is described. The first operational amplifier ( 11) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. An ion sensor (17) coupled to the positive terminal of the first operational amplifier. The second operational amplifier (12) is configured as an analog buffer wherein the output terminal provides feedback to its negative input terminal. A reference electrode (18) coupled to the positive terminal of the second operational amplifier. A gain resistor (15) is coupled to the negative terminal of the third operational amplifier to configure the third operational amplifier (13) as a gain amplifier. The output voltage of third operational amplifier provides an adjusted sensitivity and direct current level of ion sensor reading

    A PROGRAMMABLE TWO-PHASE NON-OVERLAPPING CLOCK SIGNAL SELF-GENERATOR
    4.
    发明专利
    A PROGRAMMABLE TWO-PHASE NON-OVERLAPPING CLOCK SIGNAL SELF-GENERATOR 未知

    公开(公告)号：MY162256A

    公开(公告)日：2017-05-31

    申请号：MYPI20093560

    申请日：2009-08-27

    Applicant: MIMOS BERHAD

    Inventor： WEE LEONG SON ,  YUZMAN YUSOFF

    IPC: G06F1/06 ,  G06F7/487 ,  H03K5/15

    Abstract: THE PRESENT INVENTION RELATES TO A CLOCK GENERATOR CIRCUIT (300) THAT IS PROGRAMMABLE AND CAPABLE OF SELF-GENERATING TWO-PHASE NON-OVERLAPPING CLOCK SIGNALS FOR SWITCH CAPACITOR CIRCUIT APPLICATIONS. THIS CLOCK GENERATOR CIRCUIT (300) HAS A WIDE FREQUENCY RANGE AND ALLOWS FOR SELECTION OF SEVERAL FREQUENCY RATES BY CONTROLLING THE DIGITAL INPUTS OF A MULTIPLEXER (330). BESIDES THE MULTIPLEXER (330), THE PROPOSED CIRCUIT INCLUDES A RING OSCILLATOR (310), FREQUENCY DIVIDERS (320) AND A TWO-PHASE NON-OVERLAPPING CLOCK CIRCUIT (340). THE INTERNAL RING OSCILLATOR (310) GENERATES AN OSCILLATION SIGNAL AND SENDS THE SIGNAL TO THE FREQUENCY DIVIDERS (320). THESE FREQUENCY DIVIDERS (320) GENERATE SERIES OF CLOCK SIGNALS AT DIFFERENT FREQUENCIES. THROUGH THE MULTIPLEXER (330), ONE OF THE CLOCK SIGNALS IS SELECTED AND TRANSFERRED TO THE NON-OVERLAPPING CLOCK CIRCUIT (340). THE NON-OVERLAPPING CLOCK SIGNAL GENERATOR (340) INCLUDES TOGGLE FLIP-FLOP, NAND GATES, DELAY AND BUFFER CELLS. THE MOST ILLUSTRATIVE DRAWING: FIG. 3

    SYSTEM AND METHOD TO COMPENSATE TEMPORAL AND TEMPERATURE DRIFT OF ION SENSOR
    6.
    发明申请
    SYSTEM AND METHOD TO COMPENSATE TEMPORAL AND TEMPERATURE DRIFT OF ION SENSOR 审中-公开
    补偿离子传感器的时间和温度漂移的系统和方法

    公开(公告)号：WO2011065811A2

    公开(公告)日：2011-06-03

    申请号：PCT/MY2010000279

    申请日：2010-11-16

    Applicant: MIMOS BERHAD ,  NG MEI YEE ,  YUZMAN YUSOFF

    Inventor： NG MEI YEE ,  YUZMAN YUSOFF

    IPC: G01N27/414 ,  G01N27/416

    CPC classification number: G01N27/4163 ,  G01N27/4148

    Abstract: The system (100) and method (200) according to the present invention utilizes the light source (105) component in compensating thermal and time drift effect of ISFET sensor (100). A compensating circuit that has variable gain to fine-tune the slope of LED (105) drift such that it matches that of the ISFET (100) drift is applied. Thereafter, a cancellation circuit is used to cancel off the slope of time and temperature drift of the ISFET sensor (100). The LED (105) is employed due to its insensitivity to pH which results in the pH value being accurate.

    Abstract translation: 根据本发明的系统（100）和方法（200）利用光源（105）部件来补偿ISFET传感器（100）的热和时间漂移效应。 应用具有可变增益以补偿LED（105）漂移的斜率以使其与ISFET（100）漂移的斜率相匹配的补偿电路。 此后，使用消除电路来消除ISFET传感器（100）的时间斜率和温度漂移。 LED（105）由于其对pH不敏感而被使用，导致pH值准确。

    PROGRAMMABLE CLOCK FREQUENCY DOUBLER DEVICE AND METHOD
    8.
    发明申请
    PROGRAMMABLE CLOCK FREQUENCY DOUBLER DEVICE AND METHOD 审中-公开
    可编程时钟双频器件及方法

    公开(公告)号：WO2013154418A3

    公开(公告)日：2013-12-05

    申请号：PCT/MY2013000076

    申请日：2013-04-08

    Applicant: MIMOS BERHAD

    Inventor： WEE LEONG SON ,  YUZMAN YUSOFF

    IPC: G06F1/06 ,  G06F1/08 ,  G06F1/12 ,  G06F7/68 ,  H03K5/00 ,  H03L7/081

    CPC classification number: G06F1/06 ,  G06F1/08 ,  H03K5/00006

    Abstract: The present invention discloses a device and method for use in a clocking requirement, wherein the device in accordance with the preferred embodiments of the present invention aids to synchronize in the event that there are two different clock sources. The device comprises; a means for receiving frequency input clock and derive output clock frequency; a means to convert serial to parallel data and configure first frequency doubler and output selector; a means for generating a primary clock as a reference signal; a means for receiving input signals frequency doublers and driving larger output load; and a means for selecting a plurality of doubled signals from a clock driver output.

    Abstract translation: 本发明公开了一种用于时钟要求的装置和方法，其中根据本发明的优选实施例的装置有助于在存在两个不同时钟源的情况下同步。 该装置包括： 用于接收频率输入时钟并导出输出时钟频率的装置; 将串行转换为并行数据并配置第一倍频器和输出选择器的方法; 用于产生主时钟作为参考信号的装置; 用于接收输入信号频率倍增器和驱动较大输出负载的装置; 以及用于从时钟驱动器输出中选择多个双倍信号的装置。

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