公开(公告)号：GB2239375A

公开(公告)日：1991-06-26

申请号：GB9025985

申请日：1990-11-29

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  LEVINE STEPHEN N ,  PUHL LARRY C ,  CARNEY SCOTT N

IPC: H04L1/00 ,  H03G3/34 ,  H04L1/24

Abstract: There is provided a mechanism for error detection characterized by: detecting the symmetry of error distributions over adjacent time intervals and muting of a radiotelephone in response to detected loss of substantial symmetry, unless errors are attributable to valid alternative detections. It is further characterized by: detecting the symmetry of error distributions over adjacent time intervals and muting a radiotelephone as a corrective response to detected consequential asymmetry or loss of substantial symmetry (unless errors are attributable to alternative detections of valid synchronization words) and cancelling any such corrective response upon subsequent alternative detections of valid synchronization words. The invention prevents false muting of the voice signal as a result of mistaking the shorter supervisory signal for error bits.

公开(公告)号：GB2313753B

公开(公告)日：2000-11-29

申请号：GB9708372

申请日：1997-04-25

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  OLIVER JOHN P

IPC: H03G7/00 ,  H03G11/00 ,  H03M7/30

Abstract: A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

公开(公告)号：BR9902993A

公开(公告)日：2000-08-01

申请号：BR9902993

申请日：1999-07-27

Applicant: MOTOROLA INC

Inventor： OLIVER JOHN P ,  BAKER JAMES C ,  JANSSEN JOHN J

IPC: H04L25/03 ,  H04Q7/32

Abstract: The pulse-shaping look-up table with transient suppression (530) avoids hard turn-on and turn-off transients by modifying word segments of initial and final digital words during transmission of a digital data sequence. A controller (570) sends a mode signal and a digital data sequence to the pulse-shaping look-up table with transient suppression (530). A mode buffer and command block (560) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block (550) from the digital data sequence. The digital words are used by a look-up table (540) to create a sampled digital output waveform sequence. The pulse-shaping look-up table with transient suppression (530) provides an accurate output waveform sequence with reduced spectral emissions even during start-up and shut-down of digital data transmissions.

公开(公告)号：HK1000432A1

公开(公告)日：1998-03-20

申请号：HK97102039

申请日：1997-10-27

Applicant: MOTOROLA INC

Inventor： KAZECKI HENRY L ,  BAKER JAMES C

IPC: H04Q7/38 ,  H04B7/005 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L7/10 ,  H04L27/227 ,  H04L ,  H04B ,  H04J

Abstract: A differential quadrature PSK receiver (100) recovers serial data in a forward and reverse direction in time using a forward and reverse mode PLL (232) and decoder switch (108). The DQPSK receiver (100) is particularly useful for recovering a packet of serial data (Rx) having a time-varying signal level and a relatively long duration. Sync words in the packet (Rx) or adjacent packets (Ry) provide starting points from which the data is recovered. The direction in time of data recovery is dependent on the quality of the time-varying signal level in the packet (Rx).

公开(公告)号：CA2076997C

公开(公告)日：1996-12-10

申请号：CA2076997

申请日：1992-08-27

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  KAZECKI HENRY L

IPC: H04L25/03 ,  H03H21/00 ,  H04B1/10 ,  H04B1/16

Abstract: The present invention presents an apparatus and method for recovering symbols in a data packet (101) transmitted to a receiver (201) from a remote signal source (202) in a time-varying channel using multiple adaptive filtering algorithms. The symbols in the data packet (101) are recovered using an adaptive filter 203 responsive to a recursive least squares (RLS) filtering algorithm followed by a least-mean squares (LMS) filtering algorithm. The RLS filtering algorithm is used first for its fast training and fast recovery characteristics. The LMS filtering algorithm is used second for its low complexity and high stability characteristics. The switch between the RLS and the LMS filtering algorithms may be at a fixed point in time to ensure minimal filter complexity or may be adaptive responsive to the quality of an error signal (ek) processed in a coefficient determinator (307 or 309) to ensure maximum bit error rate performance and stability.

公开(公告)号：GB2271492A

公开(公告)日：1994-04-13

申请号：GB9322404

申请日：1993-01-21

Applicant: MOTOROLA INC

Inventor： LAROSA CHRISTOPHER P ,  CARNEY MICHAEL J ,  BAKER JAMES C

IPC: H04B7/26 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H04L7/04

Abstract: The present disclosure includes a discussion of a method of synchronizing a sampling clock signal to a received data signal (131). The clock recovery circuit (127) generates several clock signals (339, 341, 343, 345) at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry (127) generates error signals (347, 349, 351, 353) representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals (347, 349, 351, 353) are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit (127) then adjusts or maintains the phase of the symbol clock (139) to provide the optimal sampling phase.

公开(公告)号：CZ9302563A3

公开(公告)日：1994-03-16

申请号：CZ256393

申请日：1993-01-21

Applicant: MOTOROLA INC

Inventor： LAROSA CHRISTOPHER P ,  CARNEY MICHAEL J ,  BAKER JAMES C

IPC: H04B7/26 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H04L7/04

CPC classification number: H04L7/0337

公开(公告)号：CZ256393A3

公开(公告)日：1994-03-16

申请号：CZ256393

申请日：1993-01-21

Applicant: MOTOROLA INC

Inventor： LAROSA CHRISTOPHER P ,  CARNEY MICHAEL J ,  BAKER JAMES C

IPC: H04B7/26 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H04L7/04

Abstract: The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

公开(公告)号：CA2097058A1

公开(公告)日：1993-03-31

申请号：CA2097058

申请日：1992-08-19

Applicant: MOTOROLA INC

Inventor： KAZECKI HENRY L ,  BAKER JAMES C

IPC: H04Q7/38 ,  H04J3/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/22 ,  H04L27/227

Abstract: The present invention presents an apparatus and method for recovering symbols in a data packet (101) transmitted to a receiver from a remote signal source (204) in a time-varying channel using multiple sampling points. In a digital cellular radiotelephone TDMA system, the receiver (202) performs a complex correlation on the desired slot sync word (DSSW) and the coded digital verification color code (CDVCC) in the data packet (101), and on the adjacent slot sync word (ASSW) in an adjacent data packet (102) to produce a first, second and third optimum sampling point, respectively. The data packet (101) is divided into four regions (A, B, C and D). The symbols in each region (A, B, C and D) are serially recovered using one or more of the multiple sampling points depending on the quality of the sampling point adjacent to each region (A, B, C and D).

公开(公告)号：GB2251161A

公开(公告)日：1992-06-24

申请号：GB9123925

申请日：1991-11-11

Applicant: MOTOROLA INC

Inventor： BAKER JAMES C ,  KAZECKI HENRY L ,  GOODE STEVEN H

IPC: H04L27/00 ,  H04L27/227

Abstract: The pi /4-QPSK coherent detector of the present invention has a vector input and an output comprising recovered data in bit pair form. The pi /4-QPSK coherent detector recovers bursts of data, in a TDMA system, that has been encoded in an amplitude modulated vector's phase angle. The pi /4-QPSK coherent detector detects the pi /4-QPSK constellation of the incoming modulated signal and outputs the recovered data stream.