公开(公告)号：DE69205953D1

公开(公告)日：1995-12-14

申请号：DE69205953

申请日：1992-12-07

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H03K3/352 ,  H02H9/04 ,  H03K17/72

Abstract: A memory circuit (10) which includes a memory SCR (24) and an output SCR (32) is provided. The memory SCR is coupled between the input terminal (12) and the common terminal (16) of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal (14) and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state .