公开(公告)号：GB2253940B

公开(公告)日：1995-11-08

申请号：GB9205731

申请日：1992-03-16

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  JOHNSEN ROBERT J ,  ROBB FRANCINE Y

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/10 ,  H01L29/417

Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

公开(公告)号：GB2253940A

公开(公告)日：1992-09-23

申请号：GB9205731

申请日：1992-03-16

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  JOHNSEN ROBERT J ,  ROBB FRANCINE Y

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/10 ,  H01L29/417

Abstract: A IGFET with a low source inductance is fabricated in a die to have a maximum of two sources 29a each in contact with a region 14 which makes contact to a substrate 10 or back side of the die. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

公开(公告)号：DE69226842D1

公开(公告)日：1998-10-08

申请号：DE69226842

申请日：1992-10-19

Applicant: MOTOROLA INC

Inventor： CLARK LOWELL E ,  DAVIES ROBERT B ,  MIETUS DAVID F

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/78

Abstract: A semiconductor device having a power switch (12) and a saturation detection diode (13) formed in an upper surface of a semiconductor drift region (11) is provided. The saturation detector diode (13) and the power switch (12) are electrically coupled by the drift region (11). An external signal applied to the detector diode (13) forward biases the detector diode (13) when the drift region (11) potential is below a predetermined voltage and the detector diode (13) becomes reverse biased when the drift region (11) potential is greater than the predetermined voltage

公开(公告)号：DE69224264T2

公开(公告)日：1998-07-09

申请号：DE69224264

申请日：1992-10-19

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H01L23/58 ,  H01L27/02 ,  H03K17/082 ,  H01L25/18 ,  H01L25/16

Abstract: A method for protecting a semiconductor power die (16) has been provided. The method involves inserting an integrated circuit die (10) between the gate lead (14) of a package containing the semiconductor power die and the actual gate terminal (24) of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

公开(公告)号：DE69224264D1

公开(公告)日：1998-03-05

申请号：DE69224264

申请日：1992-10-19

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H01L23/58 ,  H01L27/02 ,  H03K17/082 ,  H01L25/18 ,  H01L25/16

Abstract: A method for protecting a semiconductor power die (16) has been provided. The method involves inserting an integrated circuit die (10) between the gate lead (14) of a package containing the semiconductor power die and the actual gate terminal (24) of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

公开(公告)号：DE69205953T2

公开(公告)日：1996-05-23

申请号：DE69205953

申请日：1992-12-07

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H03K3/352 ,  H02H9/04 ,  H03K17/72

Abstract: A memory circuit (10) which includes a memory SCR (24) and an output SCR (32) is provided. The memory SCR is coupled between the input terminal (12) and the common terminal (16) of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal (14) and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state .

公开(公告)号：DE69208297D1

公开(公告)日：1996-03-28

申请号：DE69208297

申请日：1992-07-13

Applicant: MOTOROLA INC

Inventor： CAMBOU BERTRAND F ,  DAVIES ROBERT B

IPC: H01L21/285 ,  H01L21/338 ,  H01L29/10 ,  H01L29/812

Abstract: A semiconductor device having a channel region having a first and a second portion (13a, 13b). The first and second portions of the channel region (13a, 13b) are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

公开(公告)号：DE69205953D1

公开(公告)日：1995-12-14

申请号：DE69205953

申请日：1992-12-07

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H03K3/352 ,  H02H9/04 ,  H03K17/72

Abstract: A memory circuit (10) which includes a memory SCR (24) and an output SCR (32) is provided. The memory SCR is coupled between the input terminal (12) and the common terminal (16) of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal (14) and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state .

公开(公告)号：DE69619177T2

公开(公告)日：2002-07-18

申请号：DE69619177

申请日：1996-08-22

Applicant: MOTOROLA INC

Inventor： DOW DIANN M ,  DAVIES ROBERT B ,  WILD ANDREAS A ,  ILDEREM VIDA

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

Abstract: A method for forming a graded-channel field effect transistor includes providing a substrate (10) with an overlying gate electrode (14, 16). A spacer (23) is formed on only the drain side of the electrode. A graded-channel region (36) is formed aligned to the source side of the electrode while the spacer protects the drain side of the channel region. Source/drain regions (38) are formed, the spacer is removed, and then a drain extension region (40) is formed aligned to the drain side of the electrode.

公开(公告)号：DE69232199D1

公开(公告)日：2001-12-20

申请号：DE69232199

申请日：1992-09-14

Applicant: MOTOROLA INC

Inventor： BOLAND BERNARD W ,  DAVIES ROBERT B ,  SANDERS PAUL W

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.