公开(公告)号：JPH1067296A

公开(公告)日：1998-03-10

申请号：JP18771797

申请日：1997-06-26

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  GRAY RANDELL C

IPC: B60R21/16 ,  B60R21/01 ,  B60R21/32

Abstract: PROBLEM TO BE SOLVED: To provide an air bag expansion system to generate and supply an electric current suitable for activation of a fuse and expansion of an air bag. SOLUTION: An air bag expansion system activates a fuse 74 and generates an electric current suitable to expand an air bag. A separate capacitor 48 feeds electricity to a circuit of a drive limiting control device 54 and supplies variable voltage drive to an MOS element 68 to regulate an ignition electric current of the fuse 74. A switch circuit 38 supplies gate voltage to a transistor 46 so that a capacitor 22 comes to be able to charge the capacitor 48 through an electrical connection route. The switch circuit 38 givee electrical insulation between damping voltage accumulated in the capacitor 22 to feed an electric current of the fuse 74 and the capacitor 48 to regulate an electric current to the fuse 74 from the drive limiting control device 54.

公开(公告)号：DE69716349T2

公开(公告)日：2003-03-20

申请号：DE69716349

申请日：1997-06-25

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  GRAY RANDALL C

IPC: B60R21/16 ,  B60R21/01 ,  B60R21/32

Abstract: An air bag deployment system (10) generates the proper current to activate a squib (74) and deploy an air bag. A separate capacitor (48) powers circuitry in a drive limit controller (54) for providing a variable voltage drive to a MOS device (68) to regulate squib (74) firing current. A switch circuit (38) supplies gate current to a transistor (46) such that an electrical connecting path allows a capacitor (22) to charge a capacitor (48). During squib (74) firing and air bag deployment, the switch circuit (38) provides electrical isolation between the decaying voltage stored on the capacitor (22) that powers the squib (74) current and the capacitor (48) that provides current regulation to the squib (74) from the drive limit controller (54).

公开(公告)号：DE69716349D1

公开(公告)日：2002-11-21

申请号：DE69716349

申请日：1997-06-25

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  GRAY RANDALL C

IPC: B60R21/16 ,  B60R21/01 ,  B60R21/32

Abstract: An air bag deployment system (10) generates the proper current to activate a squib (74) and deploy an air bag. A separate capacitor (48) powers circuitry in a drive limit controller (54) for providing a variable voltage drive to a MOS device (68) to regulate squib (74) firing current. A switch circuit (38) supplies gate current to a transistor (46) such that an electrical connecting path allows a capacitor (22) to charge a capacitor (48). During squib (74) firing and air bag deployment, the switch circuit (38) provides electrical isolation between the decaying voltage stored on the capacitor (22) that powers the squib (74) current and the capacitor (48) that provides current regulation to the squib (74) from the drive limit controller (54).

公开(公告)号：DE69520178D1

公开(公告)日：2001-04-05

申请号：DE69520178

申请日：1995-07-31

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  DIXON ROBERT P

IPC: H02H9/02 ,  C21B13/10 ,  H03K17/082

Abstract: A current limit circuit (10,40) for controlling a power transistor (12) has been provided. The current limit circuit (10,40) includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor (12) for providing an appropriate voltage at the gate electrode of the power transistor (12) when a load is de-coupled from the power transistor (12). This has the effect of preventing excessive transient current when the load (16) is subsequently coupled to the power transistor (12). Additionally, the current limit circuit (10,40) includes circuitry for limiting the current flowing through the power transistor (12) via a sense circuit (14) when the load (16) is coupled to a the power transistor (12).

公开(公告)号：SG45258A1

公开(公告)日：1998-01-16

申请号：SG1996002158

申请日：1988-06-16

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  WILLARD DAVID F ,  TAHERNIA OMID ,  PAGE JAMES C ,  SPIRO ALLAN I ,  LAMBRECHT FRANK E

IPC: H04Q7/16 ,  G08B3/10 ,  G08B5/22

Abstract: A paging receiver device (10) and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory (50) of the paging receiver (10). In response to a paging user's request, the digitized stored message is recalled from memory (50), reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.

公开(公告)号：CA1332184C

公开(公告)日：1994-09-27

申请号：CA564695

申请日：1988-04-21

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  WILLARD DAVID F ,  TAHERNIA OMID ,  PAGE JAMES C ,  SPIRO ALLAN I ,  LAMBRECHT FRANK E

IPC: H04Q7/16 ,  G08B3/10 ,  H04B1/16

Abstract: SUBSTITUTE REMPLACEMENT SECTION is not Present Cette Section est Absente

公开(公告)号：DE69520178T2

公开(公告)日：2001-06-21

申请号：DE69520178

申请日：1995-07-31

Applicant: MOTOROLA INC

Inventor： BENNETT PAUL T ,  DIXON ROBERT P

IPC: H02H9/02 ,  C21B13/10 ,  H03K17/082

Abstract: A current limit circuit (10,40) for controlling a power transistor (12) has been provided. The current limit circuit (10,40) includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor (12) for providing an appropriate voltage at the gate electrode of the power transistor (12) when a load is de-coupled from the power transistor (12). This has the effect of preventing excessive transient current when the load (16) is subsequently coupled to the power transistor (12). Additionally, the current limit circuit (10,40) includes circuitry for limiting the current flowing through the power transistor (12) via a sense circuit (14) when the load (16) is coupled to a the power transistor (12).

公开(公告)号：DE69224264T2

公开(公告)日：1998-07-09

申请号：DE69224264

申请日：1992-10-19

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H01L23/58 ,  H01L27/02 ,  H03K17/082 ,  H01L25/18 ,  H01L25/16

Abstract: A method for protecting a semiconductor power die (16) has been provided. The method involves inserting an integrated circuit die (10) between the gate lead (14) of a package containing the semiconductor power die and the actual gate terminal (24) of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

公开(公告)号：DE69224264D1

公开(公告)日：1998-03-05

申请号：DE69224264

申请日：1992-10-19

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H01L23/58 ,  H01L27/02 ,  H03K17/082 ,  H01L25/18 ,  H01L25/16

Abstract: A method for protecting a semiconductor power die (16) has been provided. The method involves inserting an integrated circuit die (10) between the gate lead (14) of a package containing the semiconductor power die and the actual gate terminal (24) of the semiconductor power die. As a result, any current flowing into the gate lead of the package must pass through the integrated circuit die before entering the semiconductor power die. This allows the integrated circuit die to monitor and control the semiconductor power die.

公开(公告)号：DE69205953T2

公开(公告)日：1996-05-23

申请号：DE69205953

申请日：1992-12-07

Applicant: MOTOROLA INC

Inventor： DAVIES ROBERT B ,  MIETUS DAVID F ,  BENNETT PAUL T

IPC: H03K3/352 ,  H02H9/04 ,  H03K17/72

Abstract: A memory circuit (10) which includes a memory SCR (24) and an output SCR (32) is provided. The memory SCR is coupled between the input terminal (12) and the common terminal (16) of the memory circuit wherein the input terminal is the control terminal of the output SCR and the output SCR is coupled across the output terminal (14) and the common terminal of the memory circuit. When the memory SCR latches, it functions to subsequently latch the output SCR. Because the output SCR has a greater forward operating voltage than the memory SCR and by providing a current path from the output terminal to the memory SCR, the memory SCR remains latched during the transition period of when the output SCR goes from a latched state to an unlatched state .