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公开(公告)号：WO1982002302A1
公开(公告)日：1982-07-08
申请号：PCT/US1981001450
申请日：1981-10-28
Applicant: MOTOROLA INC
Inventor： MOTOROLA INC , LUNN GERALD K , MCGINN MICHAEL
IPC: H04B01/16
CPC classification number: H03G5/28 , H03H11/481
Abstract: Un circuit (10) possede une impedance d'entree variable qui est commandee par application d'un signal d'entree en courant continu. Le circuit d'impedance variable comprend une paire de condensateurs (12, 14) couples en serie avec une paire de diodes (32, 34). Les diodes sont rendues conductrices en reponse au signal de commande en courant continu pour cour-circuiter sensiblement les deux condensateurs en serie entre eux sur les bornes d'entree (7, 18) du circuit. Lorsqu'aucun signal de commande n'est applique sur le circuit, les diodes sont non conductrices, ce qui deconnecte les condensateurs des entrees du circuit. Par consequent, la composante de reactance de l'impedance d'entree du circuit varie en reponse au signal de commande en courant continu.
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公开(公告)号：SG45287A1
公开(公告)日：1998-01-16
申请号：SG1996002781
申请日：1993-10-04
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: An AGC system for use in positive modulation schemes of video signals is provided. The AGC system utilizes an IF amplifier (12), a demodulator (14), a video amplifier (16), a gated amplifier (18) and a peak detector (20). The gated amplifier has a first, relatively fast, time constant associated therewith. The first gated amplifier, which is activated during the time interval that the black voltage appears on the video signal, is responsive to an initial reference voltage (VREFB) and to the video signal for providing an output signal to control the gain of the IF amplifier. The peak detector has a second, relatively slow, time constant associated therewith. The peak detector is used to detect the peak white voltage level of the video signal to adjust the initial reference voltage to account for fluctuations and errors in the peak white voltage level.
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公开(公告)号：DE3852441T2
公开(公告)日：1995-06-29
申请号：DE3852441
申请日：1988-07-18
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: An automatic frequency control circuit (AFC) (10) is disclosed for use in a television receiver the latter of which includes a local oscillator (LO), an intermediate frequency (IF) demodulator section, and a phase locked loop (PLL) for acquiring and phase locking onto the IF signal. The AFC circuit comprises an acquisition circuit (72) for sensing and detecting a no signal condition, an out of lock signal condition and phase locked condition. During a no signal condition the acquisition circuit enables offset (76) and clamp (70) circuits for respectively setting the nominal operating frequencies of the voltage controlled oscillator (VCO) of the PLL and the LO to the center frequency of the IF passband. Upon appearance of an IF signal the acquisition circuit enables a sweep circuit (78) as the receiver is in an out of lock condition in order to sweep the VCO downward from the passband center frequency to just above the sound carrier frequency and then sweeps the VCO frequency upwards toward the video carrier frequency. During the downward sweep of the VCO the acquisition circuit disables the phase detector of the PLL to inhibit spurious lock up. Upon the VCO phase locking to the IF signal the clamp, sweep and offset circuits are disabled while the phase detector is enabled.
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公开(公告)号：GB2217541B
公开(公告)日：1992-05-20
申请号：GB8908508
申请日：1989-04-14
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: A wideband linearized amplifier includes first and second differential amplifier sections each including differentially connected first and second pairs of transistors and a linearizing element coupled between the emitters of first ones of the second pair of transistors of each of the first and second differential amplifier sections which cancels the non-linear effects of the base-emitter junctions of the transistors of the amplifier. The bases of the first pair of transistors of the first and second differential amplifier sections are respectively coupled to differential inputs of the amplifier while the bases of the second pair of transistors of the first and second differential amplifier sections are coupled to a reference potential. The collectors of the first pair of transistors and the first transistor of the second pair of transistors of the first differential amplifier section and the collector of the second one of the second pair of transistors of the second differential amplifier section are coupled to a first output of the amplifier while the collectors of the first pair of transistors and the first one of the second pair of transistors of the second differential amplifier section and the collector of the second one of the second pair of transistors of the first differential amplifier section are coupled to a second output of the amplifier.
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公开(公告)号：DE3176846D1
公开(公告)日：1988-09-15
申请号：DE3176846
申请日：1981-10-28
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: A vertical countdown circuit in a television receiver includes a vertical countdown counter from which a slot is decoded and compared in time with the counter reset signal. When the counter is locked by the incoming vertical synchronization pulse, the counter reset signal overlaps the slot resulting in a detection of vertical coincidence. When two such detections are made, a signal is applied to the phase detector in the horizontal phase lock loop to decrease its gain and thus the bandpass characteristic of the phase lock loop to provide high noise immunity. If, on the other hand, a predetermined number of counter reset signals are received which do not overlap the slot, then a signal is applied to the phase detector which increases the current therethrough to increase its gain and to increase the bandpass characteristic of the horizontal phase lock loop to provide better pull-in characteristics.
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Patent Agency Ranking
公开(公告)号：DE3176845D1
公开(公告)日：1988-09-15
申请号：DE3176845
申请日：1981-11-27
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL , LUNN GERALD K
Abstract: A horizontal phase lock loop for use in a television receiver comprises first and second loops and a horizontal oscillator which generates a ramp signal at a frequency of twice the line frequency. The first loop locks the oscillator signal to the horizontal synchronization pulses. The oscillator output is sliced and then divided by two to achieve a fifty percent duty cycle drive waveform to the phase detector in the first loop and to a phase detector in the second loop. The second loop includes a variable slicer which operates on the oscillator ramp signal so as to lock the flyback signal generated by the horizontal output stage to the second phase detector's switching waveform. Both loops include a divide-by-two circuit which assures fifty percent duty cycle drive waveforms.
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公开(公告)号：DE3852441D1
公开(公告)日：1995-01-26
申请号：DE3852441
申请日：1988-07-18
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: An automatic frequency control circuit (AFC) (10) is disclosed for use in a television receiver the latter of which includes a local oscillator (LO), an intermediate frequency (IF) demodulator section, and a phase locked loop (PLL) for acquiring and phase locking onto the IF signal. The AFC circuit comprises an acquisition circuit (72) for sensing and detecting a no signal condition, an out of lock signal condition and phase locked condition. During a no signal condition the acquisition circuit enables offset (76) and clamp (70) circuits for respectively setting the nominal operating frequencies of the voltage controlled oscillator (VCO) of the PLL and the LO to the center frequency of the IF passband. Upon appearance of an IF signal the acquisition circuit enables a sweep circuit (78) as the receiver is in an out of lock condition in order to sweep the VCO downward from the passband center frequency to just above the sound carrier frequency and then sweeps the VCO frequency upwards toward the video carrier frequency. During the downward sweep of the VCO the acquisition circuit disables the phase detector of the PLL to inhibit spurious lock up. Upon the VCO phase locking to the IF signal the clamp, sweep and offset circuits are disabled while the phase detector is enabled.
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公开(公告)号：SG140194G
公开(公告)日：1995-01-13
申请号：SG140194
申请日：1994-09-30
Applicant: MOTOROLA INC
Inventor： LUNN GERALD K , MAIN ERIC W , MCGINN MICHAEL
Abstract: A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.
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公开(公告)号：DE3850700D1
公开(公告)日：1994-08-25
申请号：DE3850700
申请日：1988-04-28
Applicant: MOTOROLA INC
Inventor： MCGINN MICHAEL
Abstract: A steering circuit for use with a phase locked loop (PLL) includes a D-type flip flop (72) having a data and clock input terminals and first and second output terminals at which are produced complementary logic output signals, and first (80, 82, 84, 86) and second (88, 90) current sources having inputs respectively coupled to the first and second outputs of the flip flop and outputs connected to an output (92) of the steering circuit. The steering circuit is responsive to error beat note signals generated by the PLL for either sourcing or sinking first and second currents at the output thereof depending whether the input signal frequency to the PLL is greater or less than the oscillation frequency of the voltage controlled oscillator (VCO) (22) of the PLL. The output of the steering circuit is connected to the control input terminal of the VCO such that the latter is driven to lock.
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公开(公告)号：DE3685201D1
公开(公告)日：1992-06-11
申请号：DE3685201
申请日：1986-03-27
Applicant: MOTOROLA INC
Inventor： LUNN GERALD K , MAIN ERIC W , MCGINN MICHAEL
Abstract: A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.
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