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    IMAGE REMOVAL TRANSMITTER-RECEIVER AND IMAGE REMOVAL METHOD
    3.
    发明专利
    IMAGE REMOVAL TRANSMITTER-RECEIVER AND IMAGE REMOVAL METHOD 失效

    公开(公告)号：JPH11251947A

    公开(公告)日：1999-09-17

    申请号：JP36097198

    申请日：1998-12-18

    Applicant: MOTOROLA INC

    Inventor： DAVID KEVIN LABRAIS ,  MCGINN MICHAEL

    IPC: H04B1/40 ,  H03D3/00 ,  H03D7/16 ,  H03D7/18 ,  H04B1/10 ,  H04B1/26 ,  H04B1/28

    Abstract: PROBLEM TO BE SOLVED: To provide an image removal transmitter-receiver for adjusting the both of a phase and a gain and removing unrequired images. SOLUTION: During a normal operation, by two mixer circuits 28 and 34 inside a reception circuit 16, a reference signal RFIN is frequency-converted and the same phase and out-of-phase replica signals of the reference signal RFIN are provided. In a correction mode, a signal frequency generated by a transmission VCO 22 is replaced with the reference signal RFIN. A phase detection circuit 38 provides a phase difference value, it is fed back through a first switch 45 to a phase shift circuit 36 and phase separation between the two replica signals is adjusted. An amplitude detection circuit 40 provides an amplitude error value, it is fed back through a second switch 47 to the mixer circuit 34 and the gain of the two replica signals is adjusted and matched.

    6.
    发明专利
    未知

    公开(公告)号：DE3850700T2

    公开(公告)日：1995-02-02

    申请号：DE3850700

    申请日：1988-04-28

    Applicant: MOTOROLA INC

    Inventor： MCGINN MICHAEL

    IPC: H03L7/08 ,  H03L7/087 ,  H03L7/10

    Abstract: A steering circuit for use with a phase locked loop (PLL) includes a D-type flip flop (72) having a data and clock input terminals and first and second output terminals at which are produced complementary logic output signals, and first (80, 82, 84, 86) and second (88, 90) current sources having inputs respectively coupled to the first and second outputs of the flip flop and outputs connected to an output (92) of the steering circuit. The steering circuit is responsive to error beat note signals generated by the PLL for either sourcing or sinking first and second currents at the output thereof depending whether the input signal frequency to the PLL is greater or less than the oscillation frequency of the voltage controlled oscillator (VCO) (22) of the PLL. The output of the steering circuit is connected to the control input terminal of the VCO such that the latter is driven to lock.

    LINEAR FULL WAVE RECTIFIER CIRCUIT
    9.
    发明专利
    LINEAR FULL WAVE RECTIFIER CIRCUIT 未知

    公开(公告)号：DE3176101D1

    公开(公告)日：1987-05-14

    申请号：DE3176101

    申请日：1981-10-28

    Applicant: MOTOROLA INC

    Inventor： LUNN GERALD K ,  MCGINN MICHAEL ,  MAIN WILLIAM E

    IPC: H02M7/21 ,  G01R19/22 ,  H02M7/217

    Abstract: A circuit and method for producing a signal that is nearly a perfect full wave rectified version of an applied alternating signal. The circuit comprises first and second identical non-linear symmetrical rectifiers each having a respective output coupled to a current mirror circuit. In response to the alternating signal being applied to the input of the first rectifier a full wave rectified signal is produced at the output thereof to drive the current mirror such that at the output thereof, which is coupled to the output of the second rectifier, there appears a signal identical to the output from the first rectifier. This signal is utilized to produce an input signal to the second rectifier to constrain the output signal therefrom to be identical to the output signal from the current mirror circuit. The input signal to the second rectifier is thus a perfect full wave rectified version of the input signal applied to the first rectifier.

    HORIZONTAL PHASE DETECTOR GAIN CONTROL
    10.
    发明申请
    HORIZONTAL PHASE DETECTOR GAIN CONTROL 审中-公开
    水平相位检测器增益控制

    公开(公告)号：WO1982002309A1

    公开(公告)日：1982-07-08

    申请号：PCT/US1981001448

    申请日：1981-10-28

    Applicant: MOTOROLA INC

    Inventor： MOTOROLA INC ,  MCGINN MICHAEL

    IPC: H04N05/05

    CPC classification number: H04N5/12 ,  H04N5/05

    Abstract: Un circuit de decompte vertical dans un recepteur de television comprend un compteur de decomptage vertical d'ou une tranche est decodee et comparee en temps avec le signal de remise a zero du compteur. Lorsque le compteur est verrouille par l'impulsion d'arrivee de synchronisation verticale, le signal de remise a zero du compteur chevauche la tranche et il en resulte une detection de coincidence verticale. Lorsque deux de ces detections sont effectuees, un signal est applique au detecteur de phase (60) dans la boucle de verrouillage de phase horizontale pour diminuer son gain et par consequent la caracteristique de la bande passante de la boucle de verrouillage de phase obtenant ainsi une grande immunite au bruit. Si, d'autre part, un nombre predetermine de signaux de remise a zero du compteur sont recus et ne chevauchent pas la tranche, un signal est alors applique au detecteur de phase (60) qui augmente l'intensite du courant passant au travers de celui-ci pour augmenter son gain et donc augmenter la caracteristique de la bande passante de la boucle de verrouillage de phase horizontale pour obtenir de meilleures caracteristiques de rentree ou de temps d'acquisition.

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