公开(公告)号：US20220215895A1

公开(公告)日：2022-07-07

申请号：US17700085

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US11288160B2

公开(公告)日：2022-03-29

申请号：US16995246

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, Jr. ,  Niccolo′ Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/30 ,  G11C5/14 ,  G11C16/34

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

公开(公告)号：US20220068412A1

公开(公告)日：2022-03-03

申请号：US17453289

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, JR. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/32

Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.

公开(公告)号：US20220057944A1

公开(公告)日：2022-02-24

申请号：US17001121

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Kishore K. Muchherla ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device is further coupled to the processing device and to a primary power supply and a secondary power supply. The processing device is to determine, based at least in part on availability of the primary power supply to the memory device, whether to operate the memory device with a first trim tailored to data reliability or a second trim tailored to programming time. The processing device is further to operate the memory device with the determined one of the first trim or the second trim.

公开(公告)号：US20240184481A1

公开(公告)日：2024-06-06

申请号：US18441660

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Giuseppina Puzzilli ,  Saeed Sharifi Tehrani

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to receiving a read request to perform a read operation on a block of the memory device, incrementing a counter associated with the block to track a number of read operations performed on the block; setting a timer associated with the block to an initial value; determining that respective values of the counter and the timer are indicative of a minimum number of read operations performed on the block; and issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.

公开(公告)号：US20230044883A1

公开(公告)日：2023-02-09

申请号：US17971346

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/10 ,  G06F3/06

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

公开(公告)号：US20220357873A1

公开(公告)日：2022-11-10

申请号：US17872206

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mark A. Helm ,  Giuseppina Puzzilli ,  Peter Feeley ,  Yifen Liu ,  Violante Moschiano ,  Akira Goda ,  Sampath K. Ratnam

IPC: G06F3/06

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

公开(公告)号：US20220350517A1

公开(公告)日：2022-11-03

申请号：US17846462

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

公开(公告)号：US11468949B2

公开(公告)日：2022-10-11

申请号：US17200607

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Giuseppina Puzzilli ,  Niccolo′ Righetti ,  Scott A. Stoller ,  Priya Venkataraman

IPC: G11C11/00 ,  G11C16/10 ,  G11C7/04 ,  G11C16/32 ,  G11C16/26

Abstract: A method and system for temperature-dependent operations in a memory device are described. Temperature measurements of a memory device are recorded. A determination that a temperature measurement of the memory device satisfies a threshold temperature value is performed. In response to the determination, execution of a background operation in the memory device is delayed, and host system operation(s) continue to be executed in the memory device while execution of the background operation is delayed.

公开(公告)号：US11461035B2

公开(公告)日：2022-10-04

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.