公开(公告)号：US20230261072A1

公开(公告)日：2023-08-17

申请号：US17671830

申请日：2022-02-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/51 ,  H01L23/532

CPC classification number: H01L29/4236 ,  H01L23/5283 ,  H01L29/518 ,  H01L23/53238 ,  H01L29/513 ,  H01L21/76858

Abstract: A recessed gate structure includes a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; a conductive feature, filled in the recess of the recessed structure; a first functional layer, extending between the conductive feature and the recessed structure, and comprising a first element; a second functional layer, extending between the first functional layer and the conductive feature, and comprising a second element; and an interfacial layer, extending along an interface between the first functional layer and the second functional layer, and comprising the first element and the second element.

公开(公告)号：US20250125191A1

公开(公告)日：2025-04-17

申请号：US18518714

申请日：2023-11-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/16

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

公开(公告)号：US20240363346A1

公开(公告)日：2024-10-31

申请号：US18765097

申请日：2024-07-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0272 ,  H01L21/31144

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

公开(公告)号：US20240258381A1

公开(公告)日：2024-08-01

申请号：US18636545

申请日：2024-04-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76867 ,  H01L23/5283 ,  H01L23/53238 ,  H01L29/4236 ,  H01L29/513 ,  H01L29/518

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

公开(公告)号：US20230402319A1

公开(公告)日：2023-12-14

申请号：US17746737

申请日：2022-05-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L23/53266 ,  H01L21/76805 ,  H01L21/76831

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with a fluorine-catching layer. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a first conductive via structure in the first dielectric layer. The method also includes forming a second dielectric layer over the first dielectric layer and covering the first conductive via structure, and forming a fluorine-catching layer over the second dielectric layer. The method further includes forming a third dielectric layer over the fluorine-catching layer, and forming a second conductive via structure in the third dielectric layer, the fluorine-catching layer, and the second dielectric layer.

公开(公告)号：US20230261061A1

公开(公告)日：2023-08-17

申请号：US17672138

申请日：2022-02-15

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L29/40 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76846 ,  H01L29/4236

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

公开(公告)号：US20220102355A1

公开(公告)日：2022-03-31

申请号：US17550369

申请日：2021-12-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.

公开(公告)号：US20220084933A1

公开(公告)日：2022-03-17

申请号：US17533414

申请日：2021-11-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

Abstract: The present application discloses a method for fabricating a semiconductor device with metal spacers. The method includes providing a substrate; forming a plurality of plugs above the substrate; forming a plurality of metal spacers above the plurality of plugs; and, forming a plurality of air gaps positioned between the plurality of plugs; wherein the step of forming wherein the plurality of metal spacers comprises forming a first set of metal spacers, forming a second set of metal spacers, forming a third set of metal spacers, and forming a fourth set of metal spacers; wherein the second set of metal spacers is formed between the first set of metal spacers and the third set of metal spacers, and the third set of metal spacers is formed between the second set of metal spacers and the fourth set of metal spacers