公开(公告)号：US20220173041A1

公开(公告)日：2022-06-02

申请号：US17678223

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

Abstract: A method for preparing a semiconductor device structure is provided. The method includes forming a first conductive layer over a semiconductor substrate, and forming a first dielectric layer over the first conductive layer. The first conductive layer includes copper. The method also includes etching the first dielectric layer to form a first opening exposing the first conductive layer, and forming a first lining layer and a first conductive plug in the first opening. The first lining layer includes manganese, the first conductive plug includes copper, and the first conductive plug is surrounded by the first lining layer. The method further includes forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer. The second conductive layer includes copper.

公开(公告)号：US20250125190A1

公开(公告)日：2025-04-17

申请号：US18380312

申请日：2023-10-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/321 ,  H01L29/16

Abstract: The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

公开(公告)号：US20230223259A1

公开(公告)日：2023-07-13

申请号：US17571259

申请日：2022-01-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0272 ,  H01L21/31144

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

公开(公告)号：US20250140672A1

公开(公告)日：2025-05-01

申请号：US18385979

申请日：2023-11-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers is extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degree. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

公开(公告)号：US20220093545A1

公开(公告)日：2022-03-24

申请号：US17537931

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/00

Abstract: The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

公开(公告)号：US20200335486A1

公开(公告)日：2020-10-22

申请号：US16389167

申请日：2019-04-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor package and a method for preparing the same. The semiconductor package includes a lower semiconductor layer, an upper semiconductor layer, a fixturing structure, and a molding layer. The lower semiconductor layer includes an attached region and a fixturing region adjacent to the attached region. The upper semiconductor layer is disposed over the attached region. The fixturing structure is disposed adjacent to the upper semiconductor layer. The fixturing structure has at least one fixturing hole, the fixturing hole has an opening corresponding to the fixturing region, and the opening has a first width. The molding layer covers side walls of the upper semiconductor layer. The molding layer has at least one fixturing protrusion extending into the fixturing hole, the fixturing protrusion has a first expanding portion below the opening, and the first expanding portion has a second width greater than the first width.

公开(公告)号：US20250140675A1

公开(公告)日：2025-05-01

申请号：US18536605

申请日：2023-12-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers are extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degrees. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

公开(公告)号：US20240304444A1

公开(公告)日：2024-09-12

申请号：US18668432

申请日：2024-05-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0272 ,  H01L21/31144

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

公开(公告)号：US20240079321A1

公开(公告)日：2024-03-07

申请号：US18508575

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

公开(公告)号：US20230411284A1

公开(公告)日：2023-12-21

申请号：US18230182

申请日：2023-08-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-HUI SU

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L21/76895 ,  H01L21/7682 ,  H01L21/76885

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.