公开(公告)号：EP2738828A3

公开(公告)日：2017-03-29

申请号：EP13187668.2

申请日：2013-10-08

Applicant: NXP B.V.

Inventor： Daamen, Roel ,  Koops, Gerhard ,  Steeneken, Peter

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a support (1), at least three metal layers above the support, the metal layers having a top metal layer with a top plate (33) and a bottom metal layer with a bottom plate (25), dielectric material (31) between the top and bottom plates to form a capacitor (2), and plural oxide layers (9, 11, 13, 15) above the support, such oxide layers including a top oxide layer (27), each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit comprises the steps of providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.

Abstract translation: 集成电路包括支撑件（1），在支撑件上方的至少三个金属层，金属层具有顶部金属层，其具有顶板（33）和具有底板（25）的底部金属层，介电材料（ 31）在顶板和底板之间以形成电容器（2）和在支撑件上方的多个氧化物层（9,11,13,15），这些氧化物层包括顶部氧化物层（27），每个氧化物层分别覆盖 相应的金属层。 顶部氧化物层覆盖顶部金属层，并具有露出顶板的至少一部分的开口。 一种形成集成电路的方法包括以下步骤：提供具有金属和氧化物层的载体，包括底板，形成露出底板的空腔，用电介质填充空腔，施加另外的具有顶板和 进一步的氧化物层，并形成开口以暴露顶板。

公开(公告)号：EP2658126B1

公开(公告)日：2016-07-06

申请号：EP13160895.2

申请日：2013-03-25

Applicant: NXP B.V.

Inventor： Steeneken, Peter ,  Swanenberg, Maarten ,  Boezen, Hendrik ,  Koops, Gerhard ,  Bontekoe, Frans ,  Woltjer, Reinout

IPC: H04B1/44 ,  H03K17/00

CPC classification number: H04B1/44 ,  H03K17/00

公开(公告)号：EP2316789B1

公开(公告)日：2013-01-09

申请号：EP09174891.3

申请日：2009-11-03

Applicant: NXP B.V.

Inventor： Van Wingerden, Johannes ,  Verheijden, Greja Johanna Adriana Maria ,  Koops, Gerhard ,  Van Beek, Jozef Thomas Martinus

IPC: B81C1/00

CPC classification number: B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

公开(公告)号：EP2325135B1

公开(公告)日：2012-07-11

申请号：EP09176943.0

申请日：2009-11-24

Applicant: NXP B.V.

Inventor： Van Wingerden, Johannes ,  Van den Einden, Wim ,  Roosen, Harold H ,  Verheijden, Greja Johanna Adriana Maria ,  Koops, Gerhard ,  Ernur, Didem ,  Van Beek, Jozef Thomas Martinus

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81B2201/0271 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072

公开(公告)号：EP2395548A1

公开(公告)日：2011-12-14

申请号：EP10251057.5

申请日：2010-06-08

Applicant: NXP B.V.

Inventor： Boezen, Henk ,  Koops, Gerhard ,  Golubovic, Dusan ,  Krabbenborg, Benno ,  Swanenberg, Maarten Jacobus

IPC: H01L23/367

CPC classification number: H01L23/3677 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon on insulator structure (SOI) comprising a base silicon layer, a silicon substrate and an insulating layer between the base silicon layer and the silicon substrate; and an active device formed in the silicon substrate, which active device comprises an active area, the structure further comprising a thermal conductor extending from the active area to the base silicon layer.

Abstract translation: 一种绝缘体上硅结构（SOI），包括基底硅层，硅衬底和基底硅层与硅衬底之间的绝缘层; 以及形成在硅衬底中的有源器件，该有源器件包括有源区，该结构还包括从有源区延伸到基底硅层的热导体。