公开(公告)号：EP2490263A2

公开(公告)日：2012-08-22

申请号：EP12155336.6

申请日：2012-02-14

Applicant: NXP B.V.

Inventor： Golubovic, Dusan ,  Koops, Gerhard ,  Vanhoucke, Tony ,  Van Dalen, Rob

IPC: H01L27/15 ,  H01L31/12 ,  H01L31/153 ,  H01L33/34 ,  H01L31/173

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract translation: 光耦器件便于片上电流隔离。 根据各种示例性实施例，光耦合器电路包括在绝缘体层上具有硅层的绝缘体上硅衬底，在硅层中具有硅pn结的硅基发光二极管（LED），以及 硅层中的硅基光电探测器。 LED和光电检测器分别连接到硅层中的电隔离电路。 硅（LOCOS）隔离材料的局部氧化和掩埋绝缘体层将第一电路与第二电路电隔离以防止电荷载体在第一和第二电路之间移动。 LED和光电检测器以光学方式进行通信，以在电隔离电路之间传递信号。

公开(公告)号：EP2341618A1

公开(公告)日：2011-07-06

申请号：EP09180585.3

申请日：2009-12-23

Applicant: NXP B.V.

Inventor： Koops, Gerhard ,  Van Beek, Jozef Thomas Martinus

IPC: H03H9/02 ,  H03H3/007

CPC classification number: H01L41/332 ,  H03H3/0072 ,  H03H9/02259 ,  Y10S977/762 ,  Y10T29/42

Abstract: A piezo-resistive MEMS resonator comprising an anchor (12), a resonator (10) mounted on the anchor, an actuator (16) mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire (18) coupled to the resonator.

Abstract translation: 一种压阻MEMS谐振器，包括锚固件（12），安装在锚固件上的谐振器（10），安装成在谐振器上施加静电力的致动器（16），以及包括纳米线的压阻读出装置 18）耦合到谐振器。

公开(公告)号：EP2490263B1

公开(公告)日：2020-10-28

申请号：EP12155336.6

申请日：2012-02-14

Applicant: NXP B.V.

Inventor： Golubovic, Dusan ,  Koops, Gerhard ,  Vanhoucke, Tony ,  Van Dalen, Rob

IPC: H01L27/15 ,  H01L27/14 ,  H01L31/153 ,  H01L33/34 ,  H01L31/173

公开(公告)号：EP2738828A2

公开(公告)日：2014-06-04

申请号：EP13187668.2

申请日：2013-10-08

Applicant: NXP B.V.

Inventor： Daamen, Roel ,  Koops, Gerhard ,  Steeneken, Peter

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a support (1), at least three metal layers above the support, the metal layers having a top metal layer with a top plate (33) and a bottom metal layer with a bottom plate (25), dielectric material (31) between the top and bottom plates to form a capacitor (2), and plural oxide layers (9, 11, 13, 15) above the support, such oxide layers including a top oxide layer (27), each oxide layer respectively covering a corresponding metal layer. The top oxide layer covers the top metal layer and has an opening exposing at least part of the top plate. A method of forming the integrated circuit comprises the steps of providing a support with metal and oxide layers, including a bottom plate, forming a cavity exposing the bottom plate, filling the cavity with dielectric, applying a further metal layer having a top plate and a further oxide layer, and forming an opening to expose the top plate.

公开(公告)号：EP2720270A1

公开(公告)日：2014-04-16

申请号：EP13185012.5

申请日：2013-09-18

Applicant: NXP B.V.

Inventor： Heringa, Anco ,  Koops, Gerhard ,  Boksteen, Boni, Kofi ,  Ferrara, Alessandro

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/404 ,  H01L29/7835 ,  H01L29/78624

Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Abstract translation: 描述半导体器件，包括半导体器件和驱动电路的电路的实施例，以及用于操作半导体器件的方法。 在一个实施例中，半导体器件包括在衬底中形成的衬底，源极区，漏极区和漏极延伸区以及与漏极延伸区相邻的绝缘层。 绝缘层内部和之上形成栅极层和场板。 场板位于漏极延伸区域附近，并且与栅极层和源极区域电绝缘，使得电压可以独立于施加到栅极层和源极区域的电压施加到场板。 还描述了其他实施例。

公开(公告)号：EP2658126A1

公开(公告)日：2013-10-30

申请号：EP13160895.2

申请日：2013-03-25

Applicant: NXP B.V.

Inventor： Steeneken, Peter ,  Swanenberg, Maarten ,  Boezen, Hendrik ,  Koops, Gerhard ,  Bontekoe, Frans ,  Woltjer, Reinout

IPC: H03K17/00

CPC classification number: H04B1/44 ,  H03K17/00

Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

Abstract translation: 一个或多个实施例提供用于使用电容耦合在隔离和通信在不同电压域工作的电路之间进行通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。

公开(公告)号：EP2490263A3

公开(公告)日：2016-01-13

申请号：EP12155336.6

申请日：2012-02-14

Applicant: NXP B.V.

Inventor： Golubovic, Dusan ,  Koops, Gerhard ,  Vanhoucke, Tony ,  Van Dalen, Rob

IPC: H01L27/15 ,  H01L27/14 ,  H01L31/153 ,  H01L33/34 ,  H01L31/173

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

公开(公告)号：EP2402284A1

公开(公告)日：2012-01-04

申请号：EP10167760.7

申请日：2010-06-29

Applicant: NXP B.V.

Inventor： Lander, Robert James Pascoe ,  Van Beek, Jozef Thomas Martinus ,  Van Velzen, Bart ,  Koops, Gerhard ,  In'T Zandt, Michael Antoine Armand ,  Falepin, Annelies ,  Boccardi, Guillaume

IPC: B81C1/00

CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: In a first aspect, the invention provides a MEMS packaging method in which a first sacrificial etch is used to release a MEMS component by removing the sacrificial support layer beneath the MEMS component, and a second sacrificial etch is used to remove a sacrificial cover layer beneath a hermetic cover layer. In a second aspect, the invention provides a MEMS packaging method in which a hermetic cover layer is provided over a sacrificial cover layer which is then removed. A separate reinforcement cap layer is deposited over the hermetic cover layer.

Abstract translation: 在第一方面，本发明提供一种MEMS封装方法，其中使用第一牺牲蚀刻来通过去除MEMS部件下方的牺牲支撑层来释放MEMS部件，并且使用第二牺牲蚀刻来去除下面的牺牲覆盖层 密封盖层。 在第二方面，本发明提供了一种MEMS封装方法，其中将密封覆盖层设置在牺牲覆盖层上，然后将其去除。 单独的加强盖层沉积在密封盖层上。

公开(公告)号：EP2325135A1

公开(公告)日：2011-05-25

申请号：EP09176943.0

申请日：2009-11-24

Applicant: NXP B.V.

Inventor： Van Wingerden, Johannes ,  Van den Einden, Wim ,  Roosen, Harold H ,  Verheijden, Greja Johanna Adriana Maria ,  Koops, Gerhard ,  Ernur, Didem ,  Van Beek, Jozef Thomas Martinus

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81B2201/0271 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072

Abstract: A method of packaging a micro electro-mechanical structure (122) comprises forming said structure (122) on a substrate (100); depositing a sacrificial layer (130) over said structure (122); patterning the sacrificial layer (130); depositing a SIPOS (semi-insulating polycrystalline silicon) layer (140) over the patterned sacrificial layer (130); treating the SIPOS layer (140) with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer (130) through the porous layer SIPOS (140) to form a cavity (150) including said structure (122); and sealing the porous SIPOS layer (140). A device including such a packaged micro electro-mechanical structure (122) is also disclosed.

Abstract translation: 一种封装微机电结构（122）的方法，包括：形成在基片，所述结构（122）（100）; 沉积在所述结构的牺牲层（130）（122）; 图案化所述牺牲层（130）; 沉积在所述图案化的牺牲层（130）中的SIPOS（半绝缘多晶硅）层（140）; 与蚀刻剂处理SIPOS层（140）到SIPOS层转换为多孔SIPOS层，通过多孔层SIPOS（140）去除所述图案化的牺牲层（130），以形成包括所述结构的腔体（150）（122） ; 并密封该多孔SIPOS层（140）。 包括寻求封装微机电结构的装置（122）IST游离缺失盘。

公开(公告)号：EP2316789A1

公开(公告)日：2011-05-04

申请号：EP09174891.3

申请日：2009-11-03

Applicant: NXP B.V.

Inventor： Van Wingerden, Johannes ,  Verheijden, Greja Johanna Adriana Maria ,  Koops, Gerhard ,  Van Beek, Jozef Thomas Martinus

IPC: B81C1/00

CPC classification number: B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: Disclosed is a device comprising a substrate (10) carrying a microscopic structure (15) in a cavity (20) capped by a capping layer (18) comprising a material of formula SiN x H y , wherein x>1.33 and y>0. A method of forming such a device is also disclosed.

Abstract translation: 公开了一种装置，其包括在由帽状层（18）覆盖的空腔（20）中承载微观结构（15）的衬底（10），所述覆盖层包括式SiN x H y的材料，其中x> 1.33且y> 0。 还公开了一种形成这种装置的方法。