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公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US20210294764A1
公开(公告)日：2021-09-23
申请号：US16827180
申请日：2020-03-23
Applicant: NXP B.V.
Inventor： Martin Kessel
Abstract: An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.
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公开(公告)号：US20180351573A1
公开(公告)日：2018-12-06
申请号：US15612530
申请日：2017-06-02
Applicant: NXP B.V.
Inventor： Martin Kessel , Sebastian Bohn , Jörg Andreas Siemes
Abstract: Aspects of the disclosure are directed to processing signals including data exhibiting characteristics that facilitate assessment of transmission errors. As may be implemented in accordance with one or more embodiments, parameters are generated based signal transmission characteristics and are indicative of a different types of signal characteristics, including an amount of error correction that has been carried out on the signal. Two or more of the parameters are selected based on properties of signal disturbance under different reception conditions for the signal, and a degree of disturbance in the signal is predicted based on the selected parameters and signal conditions for the respective parameters at which the signal cannot be corrected. An output generated with the signal is then controlled, based on the predicted degree of disturbance and a threshold degree of disturbance.
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公开(公告)号：US09941949B2
公开(公告)日：2018-04-10
申请号：US14266379
申请日：2014-04-30
Applicant: NXP B.V.
Inventor： Martin Kessel
IPC: H04B7/08
CPC classification number: H04B7/0871 , H04B7/0817
Abstract: A method of managing wirelessly transmitted use-data in a wireless data transmission environment, the method comprising: Receiving the wirelessly transmitted use-data by a first receiver and estimating a reception quality of the use-data received by the first receiver by applying a quality criterion. In case the reception quality meets the quality criterion, the method moreover comprises using a second receiver for background scanning the wireless data transmission environment, and in case the reception quality does not meet the quality criterion, the method moreover comprises using the second receiver additionally for reception of the use-data, thus providing both receivers for a diversity reception of the use-data.
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公开(公告)号：US20170093733A1
公开(公告)日：2017-03-30
申请号：US15252034
申请日：2016-08-30
Applicant: NXP B.V.
Inventor： Martin Kessel , Sebastian Bohn , Matthias Schattka
IPC: H04L12/823 , H04L12/927 , H04L12/879
CPC classification number: H04L47/32 , H04H20/20 , H04H40/18 , H04L47/806 , H04L49/901 , H04L49/9026
Abstract: An apparatus and method are provided. A first buffer is configured to store a first packet stream, the first buffer comprising a first read pointer pointing to a first position in the first packet stream. A second buffer is configured to store a second packet stream. The second packet stream corresponds to the first packet stream and the second buffer comprises a second read pointer. A controller is configured to determine a second position in the second packet stream that corresponds to the first position in the first packet stream and adjust the second read pointer to point to the second position.
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Patent Agency Ranking
公开(公告)号：US20150092767A1
公开(公告)日：2015-04-02
申请号：US14495324
申请日：2014-09-24
Applicant: NXP B.V.
Inventor： Martin Kessel
CPC classification number: H04J3/0602 , H04H20/22 , H04H20/426 , H04J3/12 , H04L1/0047 , H04L1/20
Abstract: A receiver node for use in a digital broadcast system, comprising a receiver configured to receive a signal containing a service encoded with an error correcting code for decoding and wherein said receiver is further configured to ignore the signal during an ignore period, the node configured to use said error correcting code and the encoded service received outside the ignore period to reconstruct the part of the service ignored by the receiver.
Abstract translation: 一种用于数字广播系统的接收器节点，包括接收机，其被配置为接收包含编码有用于解码的纠错码的服务的信号，并且其中所述接收机还被配置为在忽略期间忽略所述信号，所述节点被配置为 使用所述纠错码和在忽略周期之外接收的经编码的服务来重构由接收机忽略的部分服务。
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17.发明授权公开(公告)号：US11502699B1
公开(公告)日：2022-11-15
申请号：US17357467
申请日：2021-06-24
Applicant: NXP B.V.
Inventor： Robert Rutten , Hendrik van der Ploeg , Lucien Johannes Breems , Martin Kessel , Muhammed Bolatkale , Bernard Burdiek , Manfred Zupke , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.
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公开(公告)号：US11321253B2
公开(公告)日：2022-05-03
申请号：US16827180
申请日：2020-03-23
Applicant: NXP B.V.
Inventor： Martin Kessel
Abstract: An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.
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公开(公告)号：US10243533B1
公开(公告)日：2019-03-26
申请号：US15891790
申请日：2018-02-08
Applicant: NXP B.V.
Inventor： Marco Berkhout , Fred Mostert , Massimo Ciacci , Mattheus Johan Koerts , Martin Kessel
Abstract: Aspects are directed to an amplifier circuit including a signal processing circuit and a calibration circuit. In certain specific embodiments, the signal processing circuit includes a signal combiner and a closed-loop feedback path, and the signal processing circuit is designed to provide a loop transfer function for a derived signal partly representing contributions from an audio input signal, a control or pilot signal having a target frequency range, and a calibration signal. The signal combiner is designed to combine aspects of the control or pilot signal and aspects of the audio input signal, and the calibration circuit is designed to adjust an effective gain of the derived signal in response to whether a unity-gain frequency of a signal in the closed-loop feedback path, as provided via the loop transfer function, is higher or lower than the target frequency range. Consistent therewith and in yet more specific embodiments, such an amplifier circuit can define the target frequency range relative to the transfer function and an associated unity-gain frequency.
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公开(公告)号：US20170054458A1
公开(公告)日：2017-02-23
申请号：US15239558
申请日：2016-08-17
Applicant: NXP B.V.
Inventor： Martin Kessel
CPC classification number: H04B1/0475 , H01Q7/00 , H03G3/3052 , H03G7/002 , H04B2001/0416
Abstract: A gain control apparatus for an amplifier is disclosed. The gain control apparatus configured to provide an amplifier gain control signal for setting the gain applied by the amplifier to an amplifier signal comprising an amplifier input signal amplified by the amplifier to generate an amplifier output signal. The apparatus includes a plurality of gain determination elements comprising and a gain controller configured to generate the amplifier gain control signal based on at least the first and second gain control signals.
Abstract translation: 公开了一种用于放大器的增益控制装置。 增益控制装置，被配置为提供放大器增益控制信号，用于将由放大器施加的增益设置为放大器信号，该放大器信号包括由放大器放大的放大器输入信号以产生放大器输出信号。 该装置包括多个增益确定元件，包括：增益控制器，被配置为基于至少第一和第二增益控制信号产生放大器增益控制信号。
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