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公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US09584209B2
公开(公告)日：2017-02-28
申请号：US14587572
申请日：2014-12-31
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol
IPC: H04B7/08 , H04L27/152 , G06F13/40 , H04B1/16
CPC classification number: H04B7/0885 , G06F13/40 , H04B1/16 , H04B1/40 , H04L27/152
Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.
Abstract translation: 一种无线电接收机，包括：串行数据接口，被配置为从另一无线电接收机接收串行数据信号; 时钟/数据恢复电路，被配置为从串行数据信号产生时钟信号和数据信号; 以及无线电前端，被配置为从时钟/数据恢复电路接收时钟信号以产生接收信号; 以及信号组合电路，被配置为组合接收信号和数据信号。
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公开(公告)号：US20180081841A1
公开(公告)日：2018-03-22
申请号：US15647874
申请日：2017-07-12
Applicant: NXP B.V.
Inventor： Evert-Jan Pol
IPC: G06F13/362 , G06F13/366
CPC classification number: G06F13/3625 , G06F13/1642 , G06F13/366
Abstract: An apparatus comprising: a plurality of processors, a data bus, shared by the plurality of processors, and configured to at least receive data processed by each of the plurality of processors when performing predetermined tasks, the plurality of processors and data bus comprising at least part of a hardware based real-time computing system; a controller configured to provide for control of a maximum data rate at which data is provided to the data bus for transmission thereover by at least one of the plurality of processors in performing at least one of the predetermined tasks, wherein the controller is configured to provide for a maximum data rate at least comprising an impeded rate for the at least one predetermined tasks and an unimpeded rate wherein the impeded rate is less than the unimpeded rate.
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公开(公告)号：US11616590B2
公开(公告)日：2023-03-28
申请号：US17643096
申请日：2021-12-07
Applicant: NXP B.V.
Inventor： Martin Klein , Martin Kessel , Sebastian Bohn , Manfred Zupke , Evert-Jan Pol , Hendrik van der Ploeg , Andreas Johannes Gerrits , Prince Thomas
Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.
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公开(公告)号：US10447523B2
公开(公告)日：2019-10-15
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
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Patent Agency Ranking
公开(公告)号：US20180172761A1
公开(公告)日：2018-06-21
申请号：US15841520
申请日：2017-12-14
Applicant: NXP B.V.
Inventor： Johannes Petrus Wilhelmus van Beers , Henricus Hubertus van den Berg , Richard Morren , Joannes Theodorus van der Heiden , Evert-Jan Pol
IPC: G01R31/28
CPC classification number: G01R31/2884 , G01R31/318505 , G01R31/318533 , G01R31/3187 , G01R31/31915 , G06F11/27
Abstract: An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.
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公开(公告)号：US20180013604A1
公开(公告)日：2018-01-11
申请号：US15619259
申请日：2017-06-09
Applicant: NXP B.V.
Inventor： Joerg Heinrich Walter Wenzel , Robert Rutten , Evert-Jan Pol , Jan van Sinderen , Tjeu van Ansem , Peter van de Haar
CPC classification number: H04L27/364 , H04L1/20 , H04L27/3863
Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection module; and filter the input signal in accordance with the received filter coefficients to provide the filtered output signal.
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公开(公告)号：US20160191138A1
公开(公告)日：2016-06-30
申请号：US14587572
申请日：2014-12-31
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol
IPC: H04B7/08 , H04L27/152 , H04L7/00
CPC classification number: H04B7/0885 , G06F13/40 , H04B1/16 , H04B1/40 , H04L27/152
Abstract: A radio receiver including: a serial data interface configured to receive a serial data signal from another radio receiver; a clock/data recovery circuit configured to produce a clock signal and a data signal from the serial data signal; and a radio front-end configured to receive the clock signal from the clock/data recovery circuit to produce a received signal; and signal combining circuit configured to combine the received signal and the data signal.
Abstract translation: 一种无线电接收机，包括：串行数据接口，被配置为从另一无线电接收机接收串行数据信号; 时钟/数据恢复电路，被配置为从所述串行数据信号产生时钟信号和数据信号; 以及无线电前端，被配置为从时钟/数据恢复电路接收时钟信号以产生接收信号; 以及信号组合电路，被配置为组合接收信号和数据信号。
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公开(公告)号：US20220200718A1
公开(公告)日：2022-06-23
申请号：US17643096
申请日：2021-12-07
Applicant: NXP B.V.
Inventor： Martin Klein , Martin Kessel , Sebastian Bohn , Manfred Zupke , Evert-Jan Pol , Hendrik van der Ploeg , Andreas Johannes Gerrits , Prince Thomas
IPC: H04J3/06
Abstract: A system (100) comprising: a first unit (104) and one or more second units (104). The first unit (102) comprises: a timing reference (114) configured to provide a master-timing-reference-signal; a master time block configured to provide a master-time-signal (117) for the first unit (102) based on the master-timing-reference-signal; and a first interface (122) configured to: receive timestamped-processed-second-RF-signals from the one or more second units (104); and provide a first-unit-timing-signal (262) to the one or more second units (104) based on the master-time-signal. The one or more second units (104) each comprise: a slave time block (141) configured to: determine a slave-time-signal (142) for the second unit (104) based on the master-timing-reference-signal; determine one or more second-timing-values based on the slave-time-signal; determine an adjustment-time based on the first-unit-timing-signal received from the first unit (102) and the second-timing-values; and adjust the slave-time-signal based on the adjustment-time.
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公开(公告)号：US10003343B2
公开(公告)日：2018-06-19
申请号：US15404059
申请日：2017-01-11
Applicant: NXP B.V.
Inventor： Kaveh Kianush , Evert-Jan Pol , Marcel Van De Gevel
CPC classification number: H03L7/089 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/10 , H04L7/033 , H04L7/0331
Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
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